Acceleration Unit for HTTP Headers Identification in FPGA
Loading...
Date
2015
Authors
ORCID
Advisor
Referee
Mark
Journal Title
Journal ISSN
Volume Title
Publisher
Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií
Abstract
This paper presents a hardware accelerated identification of HTTP protocol headers, since HTTP is the most used protocol on the Internet. We have designed a hardware architecture, which will be used for detection of HTTP header in each packet. Architecture will be able to achieve the throughput needed for monitoring of 100 Gb/s networks. Nondeterministic finite automata and massive parallelism is used for pattern match.
Description
Citation
Proceedings of the 21st Conference STUDENT EEICT 2015. s. 34-36. ISBN 978-80-214-5148-3
http://www.feec.vutbr.cz/EEICT/
http://www.feec.vutbr.cz/EEICT/
Document type
Peer-reviewed
Document version
Published version
Date of access to the full text
Language of document
cs
Study field
Comittee
Date of acceptance
Defence
Result of defence
Document licence
© Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií