Solar Power Inverter

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234-gottwald.pdf(548.49 KB)
Date
2016
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Mark
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Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií
Abstract
Design of a solar power inverter with 1 kW output power capability is discussed in this paper. Interleaved boost topology used in the step-up stage as well as the output full-bridge stage are described. Control block utilizing Field-programmable-gate-array (FPGA) is described as well.
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Keywords
FPGA, boost converter, full-bridge converter, MPPT
Citation
Proceedings of the 22nd Conference STUDENT EEICT 2016. s. 234-236. ISBN 978-80-214-5350-0
http://www.feec.vutbr.cz/EEICT/
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Peer-reviewed
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en
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© Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií
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http://hdl.handle.net/11012/83927
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Student EEICT 2016
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