The Optimisation Of Large Scale Logical Circuits
| but.event.date | 25.04.2019 | cs |
| but.event.title | Student EEICT 2019 | cs |
| dc.contributor.author | Seda, Pavel | |
| dc.date.accessioned | 2020-04-16T07:19:36Z | |
| dc.date.available | 2020-04-16T07:19:36Z | |
| dc.date.issued | 2019 | cs |
| dc.description.abstract | In the phase of designing the logical circuits, it is essential to minimise the number of elements because it leads to the more reliable, more secure, and cheaper solution. For the logical functions with less than 4 variables, the Karnaugh maps are suitable. However, in practice, we encounter usually a much more complex function, in those cases, we could apply Boolean algebra laws directly or use the Quine-McCluskey method, which is based on their systematic use. Unfortunately, this method does not usually provide a minimal form of logical function for really large scale logical functions, and in a result may be redundant expressions. For that reason, we show that we could apply an additional phase which leads to the set covering problem which needs to cover all the inputs by the obtained outputs. Since this problem is N P-hard, it is necessary to use heuristic methods, such as simulated annealing. | en |
| dc.format | text | cs |
| dc.format.extent | 469-473 | cs |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.citation | Proceedings of the 25st Conference STUDENT EEICT 2019. s. 469-473. ISBN 978-80-214-5735-5 | cs |
| dc.identifier.isbn | 978-80-214-5735-5 | |
| dc.identifier.uri | http://hdl.handle.net/11012/186717 | |
| dc.language.iso | en | cs |
| dc.publisher | Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií | cs |
| dc.relation.ispartof | Proceedings of the 25st Conference STUDENT EEICT 2019 | en |
| dc.relation.uri | http://www.feec.vutbr.cz/EEICT/ | cs |
| dc.rights | © Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií | cs |
| dc.rights.access | openAccess | en |
| dc.subject | logic circuits | en |
| dc.subject | minimisation | en |
| dc.subject | set covering problem | en |
| dc.subject | simulated annealing | en |
| dc.title | The Optimisation Of Large Scale Logical Circuits | en |
| dc.type.driver | conferenceObject | en |
| dc.type.status | Peer-reviewed | en |
| dc.type.version | publishedVersion | en |
| eprints.affiliatedInstitution.department | Fakulta elektrotechniky a komunikačních technologií | cs |
Files
Original bundle
1 - 1 of 1
Loading...
- Name:
- 469_eeict2019.pdf
- Size:
- 570.94 KB
- Format:
- Adobe Portable Document Format
- Description: