Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Virtex5
OS Platform: NT64 Target Device: xc5vlx50t
Project ID (random number) b9b7a3aa2ddb4ec98125719c3fb1cf19.4FFDA24DA2BB4E7EA6749A35F58B5474.40 Target Package: ff1136
Registration ID __0_0_0 Target Speed: -1
Date Generated 2015-05-21T10:24:52 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz CPU Speed 2395 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Accumulators=2
  • 12-bit updown accumulator=2
Adders/Subtractors=11
  • 12-bit adder=1
  • 12-bit subtractor=4
  • 17-bit adder=1
  • 17-bit subtractor=2
  • 20-bit adder=2
  • 8-bit adder=1
Counters=15
  • 11-bit up counter=1
  • 12-bit up counter=4
  • 16-bit updown counter=1
  • 17-bit up counter=2
  • 24-bit up counter=2
  • 4-bit up counter=2
  • 9-bit updown counter=3
FSMs=9 ROMs=1
  • 128x1-bit ROM=1
Registers=1084
  • Flip-Flops=1084
Xors=64
  • 1-bit xor2=62
  • 1-bit xor6=2
MiscellaneousStatistics
  • AGG_BONDED_IO=61
  • AGG_IO=61
  • AGG_LOCED_IO=61
  • AGG_SLICE=842
  • NUM_BONDED_IOB=61
  • NUM_BONDED_IPAD=12
  • NUM_BONDED_OPAD=8
  • NUM_BSFULL=776
  • NUM_BSLUTONLY=648
  • NUM_BSREGONLY=522
  • NUM_BSUSED=1946
  • NUM_BUFDS=2
  • NUM_BUFG=4
  • NUM_DPRAM_O5ANDO6=8
  • NUM_GTP_DUAL=2
  • NUM_LOCED_IOB=61
  • NUM_LOCED_IPAD=12
  • NUM_LOCED_OPAD=8
  • NUM_LOGIC_O5ANDO6=109
  • NUM_LOGIC_O5ONLY=118
  • NUM_LOGIC_O6ONLY=1131
  • NUM_LUT_RT_EXO6=12
  • NUM_LUT_RT_O5=4
  • NUM_LUT_RT_O5ANDO6=2
  • NUM_LUT_RT_O6=118
  • NUM_OLOGIC=2
  • NUM_RAMB18X2=4
  • NUM_RAMB18X2_LOWER=4
  • NUM_RAMB18X2_UPPER=3
  • NUM_RAMB36_EXP=32
  • NUM_SLICEL=818
  • NUM_SLICEM=24
  • NUM_SLICE_CARRY4=111
  • NUM_SLICE_CONTROLSET=164
  • NUM_SLICE_CYINIT=1683
  • NUM_SLICE_F7MUX=53
  • NUM_SLICE_F8MUX=18
  • NUM_SLICE_FF=1298
  • NUM_SLICE_UNUSEDCTRL=312
  • NUM_SPRAM_O6ONLY=18
  • NUM_SRL_O6ONLY=26
  • NUM_TEMAC=2
  • NUM_UNUSABLE_FF_BELS=338
  • Xilinx Core blk_mem_gen_v7_3, Xilinx CORE Generator 14.7=2
  • Xilinx Core v5_emac_v1_8, Coregen 13.1=1
NetStatistics
  • NumNets_Active=2636
  • NumNets_Gnd=6
  • NumNets_Vcc=15
  • NumNodesOfType_Active_BOUNCEACROSS=305
  • NumNodesOfType_Active_BOUNCEIN=1444
  • NumNodesOfType_Active_BUFGOUT=4
  • NumNodesOfType_Active_CLKPIN=686
  • NumNodesOfType_Active_CNTRLPIN=387
  • NumNodesOfType_Active_DOUBLE=8923
  • NumNodesOfType_Active_GLOBAL=232
  • NumNodesOfType_Active_HLONG=472
  • NumNodesOfType_Active_INPUT=9081
  • NumNodesOfType_Active_IOBIN2OUT=4
  • NumNodesOfType_Active_IOBINPUT=13
  • NumNodesOfType_Active_IOBOUTPUT=17
  • NumNodesOfType_Active_OPTDELAY=195
  • NumNodesOfType_Active_OUTBOUND=3035
  • NumNodesOfType_Active_OUTPUT=2692
  • NumNodesOfType_Active_PADINPUT=13
  • NumNodesOfType_Active_PADOUTPUT=4
  • NumNodesOfType_Active_PENT=3510
  • NumNodesOfType_Active_PINBOUNCE=3003
  • NumNodesOfType_Active_PINFEED=10265
  • NumNodesOfType_Active_VLONG=392
  • NumNodesOfType_Gnd_BOUNCEACROSS=34
  • NumNodesOfType_Gnd_BOUNCEIN=570
  • NumNodesOfType_Gnd_DOUBLE=1
  • NumNodesOfType_Gnd_HGNDOUT=265
  • NumNodesOfType_Gnd_INPUT=2110
  • NumNodesOfType_Gnd_IOBINPUT=35
  • NumNodesOfType_Gnd_IOBOUTPUT=35
  • NumNodesOfType_Gnd_OUTBOUND=1
  • NumNodesOfType_Gnd_OUTPUT=1
  • NumNodesOfType_Gnd_PADINPUT=35
  • NumNodesOfType_Gnd_PINBOUNCE=920
  • NumNodesOfType_Gnd_PINFEED=2815
  • NumNodesOfType_Vcc_BOUNCEIN=128
  • NumNodesOfType_Vcc_CLKPIN=128
  • NumNodesOfType_Vcc_CNTRLPIN=14
  • NumNodesOfType_Vcc_HVCCOUT=64
  • NumNodesOfType_Vcc_INPUT=451
  • NumNodesOfType_Vcc_IOBINPUT=1
  • NumNodesOfType_Vcc_IOBOUTPUT=1
  • NumNodesOfType_Vcc_KVCCOUT=184
  • NumNodesOfType_Vcc_PADINPUT=1
  • NumNodesOfType_Vcc_PINBOUNCE=180
  • NumNodesOfType_Vcc_PINFEED=623
SiteStatistics
  • BUFG-BUFGCTRL=4
  • IOB-IOBM=31
  • IOB-IOBS=30
  • RAMB18X2-RAMBFIFO36=4
  • RAMB36_EXP-RAMBFIFO36=32
  • SLICEL-SLICEM=228
SiteSummary
  • BUFDS=2
  • BUFDS_BUFDS=2
  • BUFG=4
  • BUFG_BUFG=4
  • GTP_DUAL=2
  • GTP_DUAL_GTP_DUAL=2
  • IOB=61
  • IOB_IINV=1
  • IOB_INBUF=16
  • IOB_OUTBUF=47
  • IOB_PAD=61
  • IPAD=12
  • IPAD_IPAD=12
  • IPAD_PAD=12
  • OLOGIC=2
  • OLOGIC_O1USED=2
  • OPAD=8
  • OPAD_OPAD=8
  • OPAD_PAD=8
  • RAMB18X2=4
  • RAMB18X2_RAMB18X2_LOWER=4
  • RAMB18X2_RAMB18X2_UPPER=3
  • RAMB36_EXP=32
  • RAMB36_EXP_RAMB36_EXP=32
  • SLICEL=818
  • SLICEL_A5LUT=71
  • SLICEL_A6LUT=458
  • SLICEL_AFF=388
  • SLICEL_B5LUT=61
  • SLICEL_B6LUT=304
  • SLICEL_BFF=289
  • SLICEL_C5LUT=55
  • SLICEL_C6LUT=269
  • SLICEL_CARRY4=111
  • SLICEL_CFF=279
  • SLICEL_CYINITGND=9
  • SLICEL_CYINITVCC=9
  • SLICEL_D5LUT=46
  • SLICEL_D6LUT=340
  • SLICEL_DFF=298
  • SLICEL_F7AMUX=23
  • SLICEL_F7BMUX=30
  • SLICEL_F8MUX=18
  • SLICEM=24
  • SLICEM_A5LUT=2
  • SLICEM_A6LUT=22
  • SLICEM_AFF=20
  • SLICEM_B5LUT=2
  • SLICEM_B6LUT=13
  • SLICEM_BFF=11
  • SLICEM_C5LUT=2
  • SLICEM_C6LUT=9
  • SLICEM_CFF=7
  • SLICEM_D5LUT=2
  • SLICEM_D6LUT=9
  • SLICEM_DFF=6
  • TEMAC=2
  • TEMAC_TEMAC=2
 
Configuration Data
BSCAN_BSCAN
  • JTAG_CHAIN=[1:1]
GTP_DUAL
  • DCLK=[DCLK_INV:0] [DCLK:2]
  • RXUSRCLK0=[RXUSRCLK0:2] [RXUSRCLK0_INV:0]
  • RXUSRCLK1=[RXUSRCLK1:2] [RXUSRCLK1_INV:0]
  • RXUSRCLK20=[RXUSRCLK20:2] [RXUSRCLK20_INV:0]
  • RXUSRCLK21=[RXUSRCLK21:2] [RXUSRCLK21_INV:0]
  • TXUSRCLK0=[TXUSRCLK0_INV:0] [TXUSRCLK0:2]
  • TXUSRCLK1=[TXUSRCLK1:2] [TXUSRCLK1_INV:0]
  • TXUSRCLK20=[TXUSRCLK20_INV:0] [TXUSRCLK20:2]
  • TXUSRCLK21=[TXUSRCLK21_INV:0] [TXUSRCLK21:2]
GTP_DUAL_GTP_DUAL
  • AC_CAP_DIS_0=[TRUE:2]
  • AC_CAP_DIS_1=[TRUE:2]
  • ALIGN_COMMA_WORD_0=[1:2]
  • ALIGN_COMMA_WORD_1=[1:2]
  • CHAN_BOND_1_MAX_SKEW_0=[7:2]
  • CHAN_BOND_1_MAX_SKEW_1=[7:2]
  • CHAN_BOND_2_MAX_SKEW_0=[7:2]
  • CHAN_BOND_2_MAX_SKEW_1=[7:2]
  • CHAN_BOND_LEVEL_0=[0:2]
  • CHAN_BOND_LEVEL_1=[0:2]
  • CHAN_BOND_MODE_0=[OFF:2]
  • CHAN_BOND_MODE_1=[OFF:2]
  • CHAN_BOND_SEQ_2_USE_0=[FALSE:2]
  • CHAN_BOND_SEQ_2_USE_1=[FALSE:2]
  • CHAN_BOND_SEQ_LEN_0=[1:2]
  • CHAN_BOND_SEQ_LEN_1=[1:2]
  • CLK25_DIVIDER=[5:2]
  • CLKINDC_B=[TRUE:2]
  • CLK_CORRECT_USE_0=[TRUE:2]
  • CLK_CORRECT_USE_1=[TRUE:2]
  • CLK_COR_ADJ_LEN_0=[2:2]
  • CLK_COR_ADJ_LEN_1=[2:2]
  • CLK_COR_DET_LEN_0=[2:2]
  • CLK_COR_DET_LEN_1=[2:2]
  • CLK_COR_INSERT_IDLE_FLAG_0=[FALSE:2]
  • CLK_COR_INSERT_IDLE_FLAG_1=[FALSE:2]
  • CLK_COR_KEEP_IDLE_0=[FALSE:2]
  • CLK_COR_KEEP_IDLE_1=[FALSE:2]
  • CLK_COR_MAX_LAT_0=[18:2]
  • CLK_COR_MAX_LAT_1=[18:2]
  • CLK_COR_MIN_LAT_0=[16:2]
  • CLK_COR_MIN_LAT_1=[16:2]
  • CLK_COR_PRECEDENCE_0=[TRUE:2]
  • CLK_COR_PRECEDENCE_1=[TRUE:2]
  • CLK_COR_REPEAT_WAIT_0=[0:2]
  • CLK_COR_REPEAT_WAIT_1=[0:2]
  • CLK_COR_SEQ_2_USE_0=[TRUE:2]
  • CLK_COR_SEQ_2_USE_1=[TRUE:2]
  • COMMA_DOUBLE_0=[FALSE:2]
  • COMMA_DOUBLE_1=[FALSE:2]
  • DCLK=[DCLK_INV:0] [DCLK:2]
  • DEC_MCOMMA_DETECT_0=[TRUE:2]
  • DEC_MCOMMA_DETECT_1=[TRUE:2]
  • DEC_PCOMMA_DETECT_0=[TRUE:2]
  • DEC_PCOMMA_DETECT_1=[TRUE:2]
  • DEC_VALID_COMMA_ONLY_0=[FALSE:2]
  • DEC_VALID_COMMA_ONLY_1=[FALSE:2]
  • MCOMMA_DETECT_0=[TRUE:2]
  • MCOMMA_DETECT_1=[TRUE:2]
  • OOB_CLK_DIVIDER=[4:2]
  • OVERSAMPLE_MODE=[FALSE:2]
  • PCI_EXPRESS_MODE_0=[FALSE:2]
  • PCI_EXPRESS_MODE_1=[FALSE:2]
  • PCOMMA_DETECT_0=[TRUE:2]
  • PCOMMA_DETECT_1=[TRUE:2]
  • PLL_DIVSEL_FB=[2:2]
  • PLL_DIVSEL_REF=[1:2]
  • PLL_RXDIVSEL_OUT_0=[2:2]
  • PLL_RXDIVSEL_OUT_1=[2:2]
  • PLL_SATA_0=[FALSE:2]
  • PLL_SATA_1=[FALSE:2]
  • PLL_STARTUP_EN=[TRUE:2]
  • PLL_TXDIVSEL_COMM_OUT=[1:2]
  • PLL_TXDIVSEL_OUT_0=[2:2]
  • PLL_TXDIVSEL_OUT_1=[2:2]
  • RCV_TERM_GND_0=[FALSE:2]
  • RCV_TERM_GND_1=[FALSE:2]
  • RCV_TERM_MID_0=[FALSE:2]
  • RCV_TERM_MID_1=[FALSE:2]
  • RCV_TERM_VTTRX_0=[FALSE:2]
  • RCV_TERM_VTTRX_1=[FALSE:2]
  • RXUSRCLK0=[RXUSRCLK0:2] [RXUSRCLK0_INV:0]
  • RXUSRCLK1=[RXUSRCLK1:2] [RXUSRCLK1_INV:0]
  • RXUSRCLK20=[RXUSRCLK20:2] [RXUSRCLK20_INV:0]
  • RXUSRCLK21=[RXUSRCLK21:2] [RXUSRCLK21_INV:0]
  • RX_BUFFER_USE_0=[TRUE:2]
  • RX_BUFFER_USE_1=[TRUE:2]
  • RX_CDR_FORCE_ROTATE_0=[FALSE:2]
  • RX_CDR_FORCE_ROTATE_1=[FALSE:2]
  • RX_DECODE_SEQ_MATCH_0=[TRUE:2]
  • RX_DECODE_SEQ_MATCH_1=[TRUE:2]
  • RX_LOSS_OF_SYNC_FSM_0=[FALSE:2]
  • RX_LOSS_OF_SYNC_FSM_1=[FALSE:2]
  • RX_LOS_INVALID_INCR_0=[8:2]
  • RX_LOS_INVALID_INCR_1=[8:2]
  • RX_LOS_THRESHOLD_0=[128:2]
  • RX_LOS_THRESHOLD_1=[128:2]
  • RX_SLIDE_MODE_0=[PCS:2]
  • RX_SLIDE_MODE_1=[PCS:2]
  • RX_STATUS_FMT_0=[PCIE:2]
  • RX_STATUS_FMT_1=[PCIE:2]
  • RX_XCLK_SEL_0=[RXREC:2]
  • RX_XCLK_SEL_1=[RXREC:2]
  • SATA_MAX_BURST_0=[9:2]
  • SATA_MAX_BURST_1=[9:2]
  • SATA_MAX_INIT_0=[27:2]
  • SATA_MAX_INIT_1=[27:2]
  • SATA_MAX_WAKE_0=[9:2]
  • SATA_MAX_WAKE_1=[9:2]
  • SATA_MIN_BURST_0=[5:2]
  • SATA_MIN_BURST_1=[5:2]
  • SATA_MIN_INIT_0=[15:2]
  • SATA_MIN_INIT_1=[15:2]
  • SATA_MIN_WAKE_0=[5:2]
  • SATA_MIN_WAKE_1=[5:2]
  • SYS_CLK_EN=[FALSE:2]
  • TERMINATION_IMP_0=[50:2]
  • TERMINATION_IMP_1=[50:2]
  • TERMINATION_OVRD=[FALSE:2]
  • TXOUTCLK_SEL_0=[0:2]
  • TXOUTCLK_SEL_1=[0:2]
  • TXUSRCLK0=[TXUSRCLK0_INV:0] [TXUSRCLK0:2]
  • TXUSRCLK1=[TXUSRCLK1:2] [TXUSRCLK1_INV:0]
  • TXUSRCLK20=[TXUSRCLK20_INV:0] [TXUSRCLK20:2]
  • TXUSRCLK21=[TXUSRCLK21_INV:0] [TXUSRCLK21:2]
  • TX_BUFFER_USE_0=[TRUE:2]
  • TX_BUFFER_USE_1=[TRUE:2]
  • TX_DIFF_BOOST_0=[TRUE:2]
  • TX_DIFF_BOOST_1=[TRUE:2]
  • TX_SYNC_FILTERB=[1:2]
  • TX_XCLK_SEL_0=[TXOUT:2]
  • TX_XCLK_SEL_1=[TXOUT:2]
OLOGIC
  • D1=[D1:0] [D1_INV:2]
OLOGIC_O1USED
  • 0=[0:0] [0_INV:2]
RAMB18X2
  • CLKAL=[CLKAL_INV:0] [CLKAL:4]
  • CLKAU=[CLKAU:3] [CLKAU_INV:0]
  • CLKBL=[CLKBL:4] [CLKBL_INV:0]
  • CLKBU=[CLKBU:3] [CLKBU_INV:0]
  • ENAL=[ENAL_INV:0] [ENAL:4]
  • ENAU=[ENAU_INV:0] [ENAU:3]
  • ENBL=[ENBL_INV:0] [ENBL:4]
  • ENBU=[ENBU_INV:0] [ENBU:3]
  • REGCLKAL=[REGCLKAL_INV:0] [REGCLKAL:4]
  • REGCLKAU=[REGCLKAU_INV:0] [REGCLKAU:3]
  • REGCLKBL=[REGCLKBL_INV:0] [REGCLKBL:4]
  • REGCLKBU=[REGCLKBU:3] [REGCLKBU_INV:0]
  • SSRAL=[SSRAL:4] [SSRAL_INV:0]
  • SSRAU=[SSRAU:3] [SSRAU_INV:0]
  • SSRBL=[SSRBL:4] [SSRBL_INV:0]
  • SSRBU=[SSRBU:3] [SSRBU_INV:0]
RAMB18X2_RAMB18X2_LOWER
  • CLKAL=[CLKAL_INV:0] [CLKAL:4]
  • CLKBL=[CLKBL:4] [CLKBL_INV:0]
  • DOA_REG_L=[0:4]
  • DOB_REG_L=[0:4]
  • ENAL=[ENAL_INV:0] [ENAL:4]
  • ENBL=[ENBL_INV:0] [ENBL:4]
  • READ_WIDTH_A_L=[9:4]
  • READ_WIDTH_B_L=[9:3] [18:1]
  • REGCLKAL=[REGCLKAL_INV:0] [REGCLKAL:4]
  • REGCLKBL=[REGCLKBL_INV:0] [REGCLKBL:4]
  • SAVEDATA_L=[FALSE:4]
  • SSRAL=[SSRAL:4] [SSRAL_INV:0]
  • SSRBL=[SSRBL:4] [SSRBL_INV:0]
  • WRITE_MODE_A_L=[WRITE_FIRST:1] [READ_FIRST:3]
  • WRITE_MODE_B_L=[WRITE_FIRST:1] [READ_FIRST:3]
  • WRITE_WIDTH_A_L=[9:4]
  • WRITE_WIDTH_B_L=[9:3] [18:1]
RAMB18X2_RAMB18X2_UPPER
  • CLKAU=[CLKAU:3] [CLKAU_INV:0]
  • CLKBU=[CLKBU:3] [CLKBU_INV:0]
  • DOA_REG_U=[0:3]
  • DOB_REG_U=[0:3]
  • ENAU=[ENAU_INV:0] [ENAU:3]
  • ENBU=[ENBU_INV:0] [ENBU:3]
  • READ_WIDTH_A_U=[9:3]
  • READ_WIDTH_B_U=[9:3]
  • REGCLKAU=[REGCLKAU_INV:0] [REGCLKAU:3]
  • REGCLKBU=[REGCLKBU:3] [REGCLKBU_INV:0]
  • SAVEDATA_U=[FALSE:3]
  • SSRAU=[SSRAU:3] [SSRAU_INV:0]
  • SSRBU=[SSRBU:3] [SSRBU_INV:0]
  • WRITE_MODE_A_U=[READ_FIRST:3]
  • WRITE_MODE_B_U=[READ_FIRST:3]
  • WRITE_WIDTH_A_U=[9:3]
  • WRITE_WIDTH_B_U=[9:3]
RAMB36_EXP
  • CLKAL=[CLKAL_INV:0] [CLKAL:32]
  • CLKAU=[CLKAU:32] [CLKAU_INV:0]
  • CLKBL=[CLKBL:32] [CLKBL_INV:0]
  • CLKBU=[CLKBU:32] [CLKBU_INV:0]
  • ENAL=[ENAL_INV:0] [ENAL:32]
  • ENAU=[ENAU_INV:0] [ENAU:32]
  • ENBL=[ENBL_INV:0] [ENBL:32]
  • ENBU=[ENBU_INV:0] [ENBU:32]
  • REGCLKAL=[REGCLKAL_INV:32] [REGCLKAL:0]
  • REGCLKAU=[REGCLKAU_INV:32] [REGCLKAU:0]
  • REGCLKBL=[REGCLKBL_INV:32] [REGCLKBL:0]
  • REGCLKBU=[REGCLKBU:0] [REGCLKBU_INV:32]
  • SSRAL=[SSRAL:32] [SSRAL_INV:0]
  • SSRAU=[SSRAU:32] [SSRAU_INV:0]
  • SSRBL=[SSRBL:32] [SSRBL_INV:0]
  • SSRBU=[SSRBU:32] [SSRBU_INV:0]
RAMB36_EXP_RAMB36_EXP
  • CLKAL=[CLKAL_INV:0] [CLKAL:32]
  • CLKAU=[CLKAU:32] [CLKAU_INV:0]
  • CLKBL=[CLKBL:32] [CLKBL_INV:0]
  • CLKBU=[CLKBU:32] [CLKBU_INV:0]
  • DOA_REG=[0:32]
  • DOB_REG=[0:32]
  • ENAL=[ENAL_INV:0] [ENAL:32]
  • ENAU=[ENAU_INV:0] [ENAU:32]
  • ENBL=[ENBL_INV:0] [ENBL:32]
  • ENBU=[ENBU_INV:0] [ENBU:32]
  • RAM_EXTENSION_A=[NONE:32]
  • RAM_EXTENSION_B=[NONE:32]
  • READ_WIDTH_A=[9:32]
  • READ_WIDTH_B=[9:32]
  • REGCLKAL=[REGCLKAL_INV:32] [REGCLKAL:0]
  • REGCLKAU=[REGCLKAU_INV:32] [REGCLKAU:0]
  • REGCLKBL=[REGCLKBL_INV:32] [REGCLKBL:0]
  • REGCLKBU=[REGCLKBU:0] [REGCLKBU_INV:32]
  • SAVEDATA=[FALSE:32]
  • SSRAL=[SSRAL:32] [SSRAL_INV:0]
  • SSRAU=[SSRAU:32] [SSRAU_INV:0]
  • SSRBL=[SSRBL:32] [SSRBL_INV:0]
  • SSRBU=[SSRBU:32] [SSRBU_INV:0]
  • WRITE_MODE_A=[READ_FIRST:32]
  • WRITE_MODE_B=[READ_FIRST:32]
  • WRITE_WIDTH_A=[9:32]
  • WRITE_WIDTH_B=[9:32]
SLICEL
  • CLK=[CLK:506] [CLK_INV:0]
SLICEL_AFF
  • AFFINIT=[INIT0:376] [INIT1:12]
  • AFFSR=[SRLOW:380] [SRHIGH:8]
  • CK=[CK:388] [CK_INV:0]
  • LATCH_OR_FF=[FF:388]
  • SYNC_ATTR=[ASYNC:250] [SYNC:138]
SLICEL_BFF
  • BFFINIT=[INIT0:285] [INIT1:4]
  • BFFSR=[SRLOW:287] [SRHIGH:2]
  • CK=[CK:289] [CK_INV:0]
  • LATCH_OR_FF=[FF:289]
  • SYNC_ATTR=[ASYNC:194] [SYNC:95]
SLICEL_CFF
  • CFFINIT=[INIT0:277] [INIT1:2]
  • CFFSR=[SRLOW:278] [SRHIGH:1]
  • CK=[CK:279] [CK_INV:0]
  • LATCH_OR_FF=[FF:279]
  • SYNC_ATTR=[ASYNC:190] [SYNC:89]
SLICEL_DFF
  • CK=[CK:298] [CK_INV:0]
  • DFFINIT=[INIT0:289] [INIT1:9]
  • DFFSR=[SRLOW:294] [SRHIGH:4]
  • LATCH_OR_FF=[FF:298]
  • SYNC_ATTR=[ASYNC:192] [SYNC:106]
SLICEM
  • CLK=[CLK:24] [CLK_INV:0]
SLICEM_A5LUT
  • A5RAMMODE=[DPRAM32:2]
  • CLK=[CLK:2] [CLK_INV:0]
  • LUT_OR_MEM=[RAM:2]
SLICEM_A6LUT
  • A6RAMMODE=[SPRAM64:4] [SRL16:16] [DPRAM32:2]
  • CLK=[CLK:22] [CLK_INV:0]
  • LUT_OR_MEM=[RAM:22]
SLICEM_AFF
  • AFFINIT=[INIT0:19] [INIT1:1]
  • AFFSR=[SRLOW:20]
  • CK=[CK:20] [CK_INV:0]
  • LATCH_OR_FF=[FF:20]
  • SYNC_ATTR=[ASYNC:20]
SLICEM_B5LUT
  • B5RAMMODE=[DPRAM32:2]
  • CLK=[CLK:2] [CLK_INV:0]
  • LUT_OR_MEM=[RAM:2]
SLICEM_B6LUT
  • B6RAMMODE=[SPRAM64:4] [SRL16:7] [DPRAM32:2]
  • CLK=[CLK:13] [CLK_INV:0]
  • LUT_OR_MEM=[RAM:13]
SLICEM_BFF
  • BFFINIT=[INIT0:11]
  • BFFSR=[SRLOW:11]
  • CK=[CK:11] [CK_INV:0]
  • LATCH_OR_FF=[FF:11]
  • SYNC_ATTR=[ASYNC:11]
SLICEM_C5LUT
  • C5RAMMODE=[DPRAM32:2]
  • CLK=[CLK:2] [CLK_INV:0]
  • LUT_OR_MEM=[RAM:2]
SLICEM_C6LUT
  • C6RAMMODE=[SPRAM64:5] [SRL16:2] [DPRAM32:2]
  • CLK=[CLK:9] [CLK_INV:0]
  • LUT_OR_MEM=[RAM:9]
SLICEM_CFF
  • CFFINIT=[INIT0:7]
  • CFFSR=[SRLOW:7]
  • CK=[CK:7] [CK_INV:0]
  • LATCH_OR_FF=[FF:7]
  • SYNC_ATTR=[ASYNC:7]
SLICEM_D5LUT
  • CLK=[CLK:2] [CLK_INV:0]
  • D5RAMMODE=[DPRAM32:2]
  • LUT_OR_MEM=[RAM:2]
SLICEM_D6LUT
  • CLK=[CLK:8] [CLK_INV:0]
  • D6RAMMODE=[SPRAM64:5] [SRL16:1] [DPRAM32:2]
  • LUT_OR_MEM=[LUT:1] [RAM:8]
SLICEM_DFF
  • CK=[CK:6] [CK_INV:0]
  • DFFINIT=[INIT0:6]
  • DFFSR=[SRLOW:6]
  • LATCH_OR_FF=[FF:6]
  • SYNC_ATTR=[ASYNC:6]
TEMAC
  • CLIENTEMAC0RXCLIENTCLKIN=[CLIENTEMAC0RXCLIENTCLKIN:2] [CLIENTEMAC0RXCLIENTCLKIN_INV:0]
  • CLIENTEMAC0TXCLIENTCLKIN=[CLIENTEMAC0TXCLIENTCLKIN:2] [CLIENTEMAC0TXCLIENTCLKIN_INV:0]
  • CLIENTEMAC1RXCLIENTCLKIN=[CLIENTEMAC1RXCLIENTCLKIN_INV:0] [CLIENTEMAC1RXCLIENTCLKIN:2]
  • CLIENTEMAC1TXCLIENTCLKIN=[CLIENTEMAC1TXCLIENTCLKIN_INV:0] [CLIENTEMAC1TXCLIENTCLKIN:2]
  • DCREMACCLK=[DCREMACCLK:2] [DCREMACCLK_INV:0]
  • HOSTCLK=[HOSTCLK_INV:0] [HOSTCLK:2]
  • PHYEMAC0GTXCLK=[PHYEMAC0GTXCLK_INV:0] [PHYEMAC0GTXCLK:2]
  • PHYEMAC0MCLKIN=[PHYEMAC0MCLKIN:2] [PHYEMAC0MCLKIN_INV:0]
  • PHYEMAC0MIITXCLK=[PHYEMAC0MIITXCLK_INV:0] [PHYEMAC0MIITXCLK:2]
  • PHYEMAC0RXCLK=[PHYEMAC0RXCLK_INV:0] [PHYEMAC0RXCLK:2]
  • PHYEMAC0TXGMIIMIICLKIN=[PHYEMAC0TXGMIIMIICLKIN:2] [PHYEMAC0TXGMIIMIICLKIN_INV:0]
  • PHYEMAC1GTXCLK=[PHYEMAC1GTXCLK:2] [PHYEMAC1GTXCLK_INV:0]
  • PHYEMAC1MCLKIN=[PHYEMAC1MCLKIN:2] [PHYEMAC1MCLKIN_INV:0]
  • PHYEMAC1MIITXCLK=[PHYEMAC1MIITXCLK:2] [PHYEMAC1MIITXCLK_INV:0]
  • PHYEMAC1RXCLK=[PHYEMAC1RXCLK_INV:0] [PHYEMAC1RXCLK:2]
  • PHYEMAC1TXGMIIMIICLKIN=[PHYEMAC1TXGMIIMIICLKIN_INV:0] [PHYEMAC1TXGMIIMIICLKIN:2]
TEMAC_TEMAC
  • CLIENTEMAC0RXCLIENTCLKIN=[CLIENTEMAC0RXCLIENTCLKIN:2] [CLIENTEMAC0RXCLIENTCLKIN_INV:0]
  • CLIENTEMAC0TXCLIENTCLKIN=[CLIENTEMAC0TXCLIENTCLKIN:2] [CLIENTEMAC0TXCLIENTCLKIN_INV:0]
  • CLIENTEMAC1RXCLIENTCLKIN=[CLIENTEMAC1RXCLIENTCLKIN_INV:0] [CLIENTEMAC1RXCLIENTCLKIN:2]
  • CLIENTEMAC1TXCLIENTCLKIN=[CLIENTEMAC1TXCLIENTCLKIN_INV:0] [CLIENTEMAC1TXCLIENTCLKIN:2]
  • DCREMACCLK=[DCREMACCLK:2] [DCREMACCLK_INV:0]
  • EMAC0_1000BASEX_ENABLE=[FALSE:2]
  • EMAC0_ADDRFILTER_ENABLE=[FALSE:2]
  • EMAC0_BYTEPHY=[FALSE:2]
  • EMAC0_CONFIGVEC_79=[TRUE:2]
  • EMAC0_GTLOOPBACK=[FALSE:2]
  • EMAC0_HOST_ENABLE=[TRUE:2]
  • EMAC0_LTCHECK_DISABLE=[FALSE:2]
  • EMAC0_MDIO_ENABLE=[TRUE:2]
  • EMAC0_PHYINITAUTONEG_ENABLE=[TRUE:2]
  • EMAC0_PHYISOLATE=[FALSE:2]
  • EMAC0_PHYLOOPBACKMSB=[FALSE:2]
  • EMAC0_PHYPOWERDOWN=[FALSE:2]
  • EMAC0_PHYRESET=[FALSE:2]
  • EMAC0_RGMII_ENABLE=[FALSE:2]
  • EMAC0_RX16BITCLIENT_ENABLE=[FALSE:2]
  • EMAC0_RXFLOWCTRL_ENABLE=[TRUE:2]
  • EMAC0_RXHALFDUPLEX=[FALSE:2]
  • EMAC0_RXINBANDFCS_ENABLE=[FALSE:2]
  • EMAC0_RXJUMBOFRAME_ENABLE=[TRUE:2]
  • EMAC0_RXRESET=[FALSE:2]
  • EMAC0_RXVLAN_ENABLE=[TRUE:2]
  • EMAC0_RX_ENABLE=[TRUE:2]
  • EMAC0_SGMII_ENABLE=[TRUE:2]
  • EMAC0_SPEED_LSB=[FALSE:2]
  • EMAC0_SPEED_MSB=[TRUE:2]
  • EMAC0_TX16BITCLIENT_ENABLE=[FALSE:2]
  • EMAC0_TXFLOWCTRL_ENABLE=[TRUE:2]
  • EMAC0_TXHALFDUPLEX=[FALSE:2]
  • EMAC0_TXIFGADJUST_ENABLE=[FALSE:2]
  • EMAC0_TXINBANDFCS_ENABLE=[FALSE:2]
  • EMAC0_TXJUMBOFRAME_ENABLE=[TRUE:2]
  • EMAC0_TXRESET=[FALSE:2]
  • EMAC0_TXVLAN_ENABLE=[TRUE:2]
  • EMAC0_TX_ENABLE=[TRUE:2]
  • EMAC0_UNIDIRECTION_ENABLE=[FALSE:2]
  • EMAC0_USECLKEN=[FALSE:2]
  • EMAC1_1000BASEX_ENABLE=[FALSE:2]
  • EMAC1_ADDRFILTER_ENABLE=[FALSE:2]
  • EMAC1_BYTEPHY=[FALSE:2]
  • EMAC1_CONFIGVEC_79=[FALSE:2]
  • EMAC1_GTLOOPBACK=[FALSE:2]
  • EMAC1_HOST_ENABLE=[FALSE:2]
  • EMAC1_LTCHECK_DISABLE=[FALSE:2]
  • EMAC1_MDIO_ENABLE=[FALSE:2]
  • EMAC1_PHYINITAUTONEG_ENABLE=[FALSE:2]
  • EMAC1_PHYISOLATE=[FALSE:2]
  • EMAC1_PHYLOOPBACKMSB=[FALSE:2]
  • EMAC1_PHYPOWERDOWN=[FALSE:2]
  • EMAC1_PHYRESET=[FALSE:2]
  • EMAC1_RGMII_ENABLE=[FALSE:2]
  • EMAC1_RX16BITCLIENT_ENABLE=[FALSE:2]
  • EMAC1_RXFLOWCTRL_ENABLE=[FALSE:2]
  • EMAC1_RXHALFDUPLEX=[FALSE:2]
  • EMAC1_RXINBANDFCS_ENABLE=[FALSE:2]
  • EMAC1_RXJUMBOFRAME_ENABLE=[FALSE:2]
  • EMAC1_RXRESET=[FALSE:2]
  • EMAC1_RXVLAN_ENABLE=[FALSE:2]
  • EMAC1_RX_ENABLE=[FALSE:2]
  • EMAC1_SGMII_ENABLE=[FALSE:2]
  • EMAC1_SPEED_LSB=[FALSE:2]
  • EMAC1_SPEED_MSB=[FALSE:2]
  • EMAC1_TX16BITCLIENT_ENABLE=[FALSE:2]
  • EMAC1_TXFLOWCTRL_ENABLE=[FALSE:2]
  • EMAC1_TXHALFDUPLEX=[FALSE:2]
  • EMAC1_TXIFGADJUST_ENABLE=[FALSE:2]
  • EMAC1_TXINBANDFCS_ENABLE=[FALSE:2]
  • EMAC1_TXJUMBOFRAME_ENABLE=[FALSE:2]
  • EMAC1_TXRESET=[FALSE:2]
  • EMAC1_TXVLAN_ENABLE=[FALSE:2]
  • EMAC1_TX_ENABLE=[FALSE:2]
  • EMAC1_UNIDIRECTION_ENABLE=[FALSE:2]
  • EMAC1_USECLKEN=[FALSE:2]
  • HOSTCLK=[HOSTCLK_INV:0] [HOSTCLK:2]
  • PHYEMAC0GTXCLK=[PHYEMAC0GTXCLK_INV:0] [PHYEMAC0GTXCLK:2]
  • PHYEMAC0MCLKIN=[PHYEMAC0MCLKIN:2] [PHYEMAC0MCLKIN_INV:0]
  • PHYEMAC0MIITXCLK=[PHYEMAC0MIITXCLK_INV:0] [PHYEMAC0MIITXCLK:2]
  • PHYEMAC0RXCLK=[PHYEMAC0RXCLK_INV:0] [PHYEMAC0RXCLK:2]
  • PHYEMAC0TXGMIIMIICLKIN=[PHYEMAC0TXGMIIMIICLKIN:2] [PHYEMAC0TXGMIIMIICLKIN_INV:0]
  • PHYEMAC1GTXCLK=[PHYEMAC1GTXCLK:2] [PHYEMAC1GTXCLK_INV:0]
  • PHYEMAC1MCLKIN=[PHYEMAC1MCLKIN:2] [PHYEMAC1MCLKIN_INV:0]
  • PHYEMAC1MIITXCLK=[PHYEMAC1MIITXCLK:2] [PHYEMAC1MIITXCLK_INV:0]
  • PHYEMAC1RXCLK=[PHYEMAC1RXCLK_INV:0] [PHYEMAC1RXCLK:2]
  • PHYEMAC1TXGMIIMIICLKIN=[PHYEMAC1TXGMIIMIICLKIN_INV:0] [PHYEMAC1TXGMIIMIICLKIN:2]
 
Pin Data
BSCAN
  • DRCK=1
  • SEL=1
  • SHIFT=1
  • TDI=1
  • TDO=1
  • UPDATE=1
BSCAN_BSCAN
  • DRCK=1
  • SEL=1
  • SHIFT=1
  • TDI=1
  • TDO=1
  • UPDATE=1
BUFDS
  • IN=2
  • IP=2
  • O=2
BUFDS_BUFDS
  • IN=2
  • IP=2
  • O=2
BUFG
  • I0=4
  • O=4
BUFG_BUFG
  • I0=4
  • O=4
GTP_DUAL
  • CLKIN=2
  • DADDR0=2
  • DADDR1=2
  • DADDR2=2
  • DADDR3=2
  • DADDR4=2
  • DADDR5=2
  • DADDR6=2
  • DCLK=2
  • DEN=2
  • DI0=2
  • DI1=2
  • DI10=2
  • DI11=2
  • DI12=2
  • DI13=2
  • DI14=2
  • DI15=2
  • DI2=2
  • DI3=2
  • DI4=2
  • DI5=2
  • DI6=2
  • DI7=2
  • DI8=2
  • DI9=2
  • DWE=2
  • GTPRESET=2
  • GTPTEST0=2
  • GTPTEST1=2
  • GTPTEST2=2
  • GTPTEST3=2
  • INTDATAWIDTH=2
  • LOOPBACK00=2
  • LOOPBACK01=2
  • LOOPBACK02=2
  • LOOPBACK10=2
  • LOOPBACK11=2
  • LOOPBACK12=2
  • PLLLKDET=2
  • PLLLKDETEN=2
  • PLLPOWERDOWN=2
  • PRBSCNTRESET0=2
  • PRBSCNTRESET1=2
  • REFCLKOUT=2
  • REFCLKPWRDNB=2
  • RXBUFRESET0=2
  • RXBUFRESET1=2
  • RXBUFSTATUS02=2
  • RXCDRRESET0=2
  • RXCDRRESET1=2
  • RXCHARISCOMMA00=2
  • RXCHARISK00=2
  • RXCHBONDI00=2
  • RXCHBONDI01=2
  • RXCHBONDI02=2
  • RXCHBONDI10=2
  • RXCHBONDI11=2
  • RXCHBONDI12=2
  • RXCLKCORCNT00=2
  • RXCLKCORCNT01=2
  • RXCLKCORCNT02=2
  • RXCOMMADETUSE0=2
  • RXCOMMADETUSE1=2
  • RXDATA00=2
  • RXDATA01=2
  • RXDATA02=2
  • RXDATA03=2
  • RXDATA04=2
  • RXDATA05=2
  • RXDATA06=2
  • RXDATA07=2
  • RXDATAWIDTH0=2
  • RXDATAWIDTH1=2
  • RXDEC8B10BUSE0=2
  • RXDEC8B10BUSE1=2
  • RXDISPERR00=2
  • RXELECIDLE0=2
  • RXELECIDLERESET0=2
  • RXELECIDLERESET1=2
  • RXENCHANSYNC0=2
  • RXENCHANSYNC1=2
  • RXENELECIDLERESETB=2
  • RXENEQB0=2
  • RXENEQB1=2
  • RXENMCOMMAALIGN0=2
  • RXENMCOMMAALIGN1=2
  • RXENPCOMMAALIGN0=2
  • RXENPCOMMAALIGN1=2
  • RXENPRBSTST00=2
  • RXENPRBSTST01=2
  • RXENPRBSTST10=2
  • RXENPRBSTST11=2
  • RXENSAMPLEALIGN0=2
  • RXENSAMPLEALIGN1=2
  • RXEQMIX00=2
  • RXEQMIX01=2
  • RXEQMIX10=2
  • RXEQMIX11=2
  • RXEQPOLE00=2
  • RXEQPOLE01=2
  • RXEQPOLE02=2
  • RXEQPOLE03=2
  • RXEQPOLE10=2
  • RXEQPOLE11=2
  • RXEQPOLE12=2
  • RXEQPOLE13=2
  • RXN0=2
  • RXN1=2
  • RXNOTINTABLE00=2
  • RXP0=2
  • RXP1=2
  • RXPMASETPHASE0=2
  • RXPMASETPHASE1=2
  • RXPOLARITY0=2
  • RXPOLARITY1=2
  • RXPOWERDOWN00=2
  • RXPOWERDOWN01=2
  • RXPOWERDOWN10=2
  • RXPOWERDOWN11=2
  • RXRESET0=2
  • RXRESET1=2
  • RXRUNDISP00=2
  • RXSLIDE0=2
  • RXSLIDE1=2
  • RXUSRCLK0=2
  • RXUSRCLK1=2
  • RXUSRCLK20=2
  • RXUSRCLK21=2
  • TXBUFDIFFCTRL00=2
  • TXBUFDIFFCTRL01=2
  • TXBUFDIFFCTRL02=2
  • TXBUFDIFFCTRL10=2
  • TXBUFDIFFCTRL11=2
  • TXBUFDIFFCTRL12=2
  • TXBUFSTATUS01=2
  • TXBYPASS8B10B00=2
  • TXBYPASS8B10B01=2
  • TXBYPASS8B10B10=2
  • TXBYPASS8B10B11=2
  • TXCHARDISPMODE00=2
  • TXCHARDISPMODE01=2
  • TXCHARDISPMODE10=2
  • TXCHARDISPMODE11=2
  • TXCHARDISPVAL00=2
  • TXCHARDISPVAL01=2
  • TXCHARDISPVAL10=2
  • TXCHARDISPVAL11=2
  • TXCHARISK00=2
  • TXCHARISK01=2
  • TXCHARISK10=2
  • TXCHARISK11=2
  • TXCOMSTART0=2
  • TXCOMSTART1=2
  • TXCOMTYPE0=2
  • TXCOMTYPE1=2
  • TXDATA00=2
  • TXDATA01=2
  • TXDATA010=2
  • TXDATA011=2
  • TXDATA012=2
  • TXDATA013=2
  • TXDATA014=2
  • TXDATA015=2
  • TXDATA02=2
  • TXDATA03=2
  • TXDATA04=2
  • TXDATA05=2
  • TXDATA06=2
  • TXDATA07=2
  • TXDATA08=2
  • TXDATA09=2
  • TXDATA10=2
  • TXDATA11=2
  • TXDATA110=2
  • TXDATA111=2
  • TXDATA112=2
  • TXDATA113=2
  • TXDATA114=2
  • TXDATA115=2
  • TXDATA12=2
  • TXDATA13=2
  • TXDATA14=2
  • TXDATA15=2
  • TXDATA16=2
  • TXDATA17=2
  • TXDATA18=2
  • TXDATA19=2
  • TXDATAWIDTH0=2
  • TXDATAWIDTH1=2
  • TXDETECTRX0=2
  • TXDETECTRX1=2
  • TXDIFFCTRL00=2
  • TXDIFFCTRL01=2
  • TXDIFFCTRL02=2
  • TXDIFFCTRL10=2
  • TXDIFFCTRL11=2
  • TXDIFFCTRL12=2
  • TXELECIDLE0=2
  • TXELECIDLE1=2
  • TXENC8B10BUSE0=2
  • TXENC8B10BUSE1=2
  • TXENPMAPHASEALIGN=2
  • TXENPRBSTST00=2
  • TXENPRBSTST01=2
  • TXENPRBSTST10=2
  • TXENPRBSTST11=2
  • TXINHIBIT0=2
  • TXINHIBIT1=2
  • TXN0=2
  • TXN1=2
  • TXP0=2
  • TXP1=2
  • TXPMASETPHASE=2
  • TXPOLARITY0=2
  • TXPOLARITY1=2
  • TXPOWERDOWN00=2
  • TXPOWERDOWN01=2
  • TXPOWERDOWN10=2
  • TXPOWERDOWN11=2
  • TXPREEMPHASIS00=2
  • TXPREEMPHASIS01=2
  • TXPREEMPHASIS02=2
  • TXPREEMPHASIS10=2
  • TXPREEMPHASIS11=2
  • TXPREEMPHASIS12=2
  • TXRESET0=2
  • TXRESET1=2
  • TXUSRCLK0=2
  • TXUSRCLK1=2
  • TXUSRCLK20=2
  • TXUSRCLK21=2
GTP_DUAL_GTP_DUAL
  • CLKIN=2
  • DADDR0=2
  • DADDR1=2
  • DADDR2=2
  • DADDR3=2
  • DADDR4=2
  • DADDR5=2
  • DADDR6=2
  • DCLK=2
  • DEN=2
  • DI0=2
  • DI1=2
  • DI10=2
  • DI11=2
  • DI12=2
  • DI13=2
  • DI14=2
  • DI15=2
  • DI2=2
  • DI3=2
  • DI4=2
  • DI5=2
  • DI6=2
  • DI7=2
  • DI8=2
  • DI9=2
  • DWE=2
  • GTPRESET=2
  • GTPTEST0=2
  • GTPTEST1=2
  • GTPTEST2=2
  • GTPTEST3=2
  • INTDATAWIDTH=2
  • LOOPBACK00=2
  • LOOPBACK01=2
  • LOOPBACK02=2
  • LOOPBACK10=2
  • LOOPBACK11=2
  • LOOPBACK12=2
  • PLLLKDET=2
  • PLLLKDETEN=2
  • PLLPOWERDOWN=2
  • PRBSCNTRESET0=2
  • PRBSCNTRESET1=2
  • REFCLKOUT=2
  • REFCLKPWRDNB=2
  • RXBUFRESET0=2
  • RXBUFRESET1=2
  • RXBUFSTATUS02=2
  • RXCDRRESET0=2
  • RXCDRRESET1=2
  • RXCHARISCOMMA00=2
  • RXCHARISK00=2
  • RXCHBONDI00=2
  • RXCHBONDI01=2
  • RXCHBONDI02=2
  • RXCHBONDI10=2
  • RXCHBONDI11=2
  • RXCHBONDI12=2
  • RXCLKCORCNT00=2
  • RXCLKCORCNT01=2
  • RXCLKCORCNT02=2
  • RXCOMMADETUSE0=2
  • RXCOMMADETUSE1=2
  • RXDATA00=2
  • RXDATA01=2
  • RXDATA02=2
  • RXDATA03=2
  • RXDATA04=2
  • RXDATA05=2
  • RXDATA06=2
  • RXDATA07=2
  • RXDATAWIDTH0=2
  • RXDATAWIDTH1=2
  • RXDEC8B10BUSE0=2
  • RXDEC8B10BUSE1=2
  • RXDISPERR00=2
  • RXELECIDLE0=2
  • RXELECIDLERESET0=2
  • RXELECIDLERESET1=2
  • RXENCHANSYNC0=2
  • RXENCHANSYNC1=2
  • RXENELECIDLERESETB=2
  • RXENEQB0=2
  • RXENEQB1=2
  • RXENMCOMMAALIGN0=2
  • RXENMCOMMAALIGN1=2
  • RXENPCOMMAALIGN0=2
  • RXENPCOMMAALIGN1=2
  • RXENPRBSTST00=2
  • RXENPRBSTST01=2
  • RXENPRBSTST10=2
  • RXENPRBSTST11=2
  • RXENSAMPLEALIGN0=2
  • RXENSAMPLEALIGN1=2
  • RXEQMIX00=2
  • RXEQMIX01=2
  • RXEQMIX10=2
  • RXEQMIX11=2
  • RXEQPOLE00=2
  • RXEQPOLE01=2
  • RXEQPOLE02=2
  • RXEQPOLE03=2
  • RXEQPOLE10=2
  • RXEQPOLE11=2
  • RXEQPOLE12=2
  • RXEQPOLE13=2
  • RXN0=2
  • RXN1=2
  • RXNOTINTABLE00=2
  • RXP0=2
  • RXP1=2
  • RXPMASETPHASE0=2
  • RXPMASETPHASE1=2
  • RXPOLARITY0=2
  • RXPOLARITY1=2
  • RXPOWERDOWN00=2
  • RXPOWERDOWN01=2
  • RXPOWERDOWN10=2
  • RXPOWERDOWN11=2
  • RXRESET0=2
  • RXRESET1=2
  • RXRUNDISP00=2
  • RXSLIDE0=2
  • RXSLIDE1=2
  • RXUSRCLK0=2
  • RXUSRCLK1=2
  • RXUSRCLK20=2
  • RXUSRCLK21=2
  • TXBUFDIFFCTRL00=2
  • TXBUFDIFFCTRL01=2
  • TXBUFDIFFCTRL02=2
  • TXBUFDIFFCTRL10=2
  • TXBUFDIFFCTRL11=2
  • TXBUFDIFFCTRL12=2
  • TXBUFSTATUS01=2
  • TXBYPASS8B10B00=2
  • TXBYPASS8B10B01=2
  • TXBYPASS8B10B10=2
  • TXBYPASS8B10B11=2
  • TXCHARDISPMODE00=2
  • TXCHARDISPMODE01=2
  • TXCHARDISPMODE10=2
  • TXCHARDISPMODE11=2
  • TXCHARDISPVAL00=2
  • TXCHARDISPVAL01=2
  • TXCHARDISPVAL10=2
  • TXCHARDISPVAL11=2
  • TXCHARISK00=2
  • TXCHARISK01=2
  • TXCHARISK10=2
  • TXCHARISK11=2
  • TXCOMSTART0=2
  • TXCOMSTART1=2
  • TXCOMTYPE0=2
  • TXCOMTYPE1=2
  • TXDATA00=2
  • TXDATA01=2
  • TXDATA010=2
  • TXDATA011=2
  • TXDATA012=2
  • TXDATA013=2
  • TXDATA014=2
  • TXDATA015=2
  • TXDATA02=2
  • TXDATA03=2
  • TXDATA04=2
  • TXDATA05=2
  • TXDATA06=2
  • TXDATA07=2
  • TXDATA08=2
  • TXDATA09=2
  • TXDATA10=2
  • TXDATA11=2
  • TXDATA110=2
  • TXDATA111=2
  • TXDATA112=2
  • TXDATA113=2
  • TXDATA114=2
  • TXDATA115=2
  • TXDATA12=2
  • TXDATA13=2
  • TXDATA14=2
  • TXDATA15=2
  • TXDATA16=2
  • TXDATA17=2
  • TXDATA18=2
  • TXDATA19=2
  • TXDATAWIDTH0=2
  • TXDATAWIDTH1=2
  • TXDETECTRX0=2
  • TXDETECTRX1=2
  • TXDIFFCTRL00=2
  • TXDIFFCTRL01=2
  • TXDIFFCTRL02=2
  • TXDIFFCTRL10=2
  • TXDIFFCTRL11=2
  • TXDIFFCTRL12=2
  • TXELECIDLE0=2
  • TXELECIDLE1=2
  • TXENC8B10BUSE0=2
  • TXENC8B10BUSE1=2
  • TXENPMAPHASEALIGN=2
  • TXENPRBSTST00=2
  • TXENPRBSTST01=2
  • TXENPRBSTST10=2
  • TXENPRBSTST11=2
  • TXINHIBIT0=2
  • TXINHIBIT1=2
  • TXN0=2
  • TXN1=2
  • TXP0=2
  • TXP1=2
  • TXPMASETPHASE=2
  • TXPOLARITY0=2
  • TXPOLARITY1=2
  • TXPOWERDOWN00=2
  • TXPOWERDOWN01=2
  • TXPOWERDOWN10=2
  • TXPOWERDOWN11=2
  • TXPREEMPHASIS00=2
  • TXPREEMPHASIS01=2
  • TXPREEMPHASIS02=2
  • TXPREEMPHASIS10=2
  • TXPREEMPHASIS11=2
  • TXPREEMPHASIS12=2
  • TXRESET0=2
  • TXRESET1=2
  • TXUSRCLK0=2
  • TXUSRCLK1=2
  • TXUSRCLK20=2
  • TXUSRCLK21=2
IOB
  • I=16
  • O=47
  • PAD=61
  • T=2
IOB_IINV
  • IN=1
  • OUT=1
IOB_INBUF
  • OUT=16
  • PAD=16
IOB_OUTBUF
  • IN=47
  • OUT=47
  • TRI=2
IOB_PAD
  • PAD=61
IPAD
  • O=12
  • PAD=12
IPAD_IPAD
  • I=12
  • O=12
IPAD_PAD
  • PAD=12
OLOGIC
  • D1=2
  • OQ=2
OLOGIC_O1USED
  • 0=2
  • OUT=2
OPAD
  • I=8
  • PAD=8
OPAD_OPAD
  • I=8
  • O=8
OPAD_PAD
  • PAD=8
RAMB18X2
  • ADDRAL10=4
  • ADDRAL11=4
  • ADDRAL12=4
  • ADDRAL13=4
  • ADDRAL14=4
  • ADDRAL15=4
  • ADDRAL4=4
  • ADDRAL5=4
  • ADDRAL6=4
  • ADDRAL7=4
  • ADDRAL8=4
  • ADDRAL9=4
  • ADDRAU10=3
  • ADDRAU11=3
  • ADDRAU12=3
  • ADDRAU13=3
  • ADDRAU14=3
  • ADDRAU4=3
  • ADDRAU5=3
  • ADDRAU6=3
  • ADDRAU7=3
  • ADDRAU8=3
  • ADDRAU9=3
  • ADDRBL10=4
  • ADDRBL11=4
  • ADDRBL12=4
  • ADDRBL13=4
  • ADDRBL14=4
  • ADDRBL15=4
  • ADDRBL4=3
  • ADDRBL5=4
  • ADDRBL6=4
  • ADDRBL7=4
  • ADDRBL8=4
  • ADDRBL9=4
  • ADDRBU10=3
  • ADDRBU11=3
  • ADDRBU12=3
  • ADDRBU13=3
  • ADDRBU14=3
  • ADDRBU4=3
  • ADDRBU5=3
  • ADDRBU6=3
  • ADDRBU7=3
  • ADDRBU8=3
  • ADDRBU9=3
  • CLKAL=4
  • CLKAU=3
  • CLKBL=4
  • CLKBU=3
  • DIAL0=4
  • DIAL1=4
  • DIAL2=4
  • DIAL3=4
  • DIAL4=4
  • DIAL5=4
  • DIAL6=4
  • DIAL7=4
  • DIAU0=3
  • DIAU1=3
  • DIAU2=3
  • DIAU3=3
  • DIAU4=3
  • DIAU5=3
  • DIAU6=3
  • DIAU7=3
  • DIBL0=4
  • DIBL1=4
  • DIBL10=1
  • DIBL11=1
  • DIBL12=1
  • DIBL13=1
  • DIBL14=1
  • DIBL15=1
  • DIBL2=4
  • DIBL3=4
  • DIBL4=4
  • DIBL5=4
  • DIBL6=4
  • DIBL7=4
  • DIBL8=1
  • DIBL9=1
  • DIBU0=3
  • DIBU1=3
  • DIBU2=3
  • DIBU3=3
  • DIBU4=3
  • DIBU5=3
  • DIBU6=3
  • DIBU7=3
  • DIPAL0=4
  • DIPAU0=3
  • DIPBL0=4
  • DIPBL1=1
  • DIPBU0=3
  • DOBL0=4
  • DOBL1=4
  • DOBL10=1
  • DOBL11=1
  • DOBL12=1
  • DOBL13=1
  • DOBL14=1
  • DOBL15=1
  • DOBL2=4
  • DOBL3=4
  • DOBL4=4
  • DOBL5=4
  • DOBL6=4
  • DOBL7=4
  • DOBL8=1
  • DOBL9=1
  • DOBU0=3
  • DOBU1=3
  • DOBU2=3
  • DOBU3=3
  • DOBU4=3
  • DOBU5=3
  • DOBU6=3
  • DOBU7=3
  • DOPBL0=4
  • DOPBL1=1
  • DOPBU0=3
  • ENAL=4
  • ENAU=3
  • ENBL=4
  • ENBU=3
  • REGCEAL=4
  • REGCEAU=3
  • REGCEBL=4
  • REGCEBU=3
  • REGCLKAL=4
  • REGCLKAU=3
  • REGCLKBL=4
  • REGCLKBU=3
  • SSRAL=4
  • SSRAU=3
  • SSRBL=4
  • SSRBU=3
  • WEAL0=4
  • WEAL1=4
  • WEAL2=4
  • WEAL3=4
  • WEAU0=3
  • WEAU1=3
  • WEAU2=3
  • WEAU3=3
  • WEBL0=4
  • WEBL1=4
  • WEBL2=4
  • WEBL3=4
  • WEBL4=4
  • WEBL5=4
  • WEBL6=4
  • WEBL7=4
  • WEBU0=3
  • WEBU1=3
  • WEBU2=3
  • WEBU3=3
  • WEBU4=3
  • WEBU5=3
  • WEBU6=3
  • WEBU7=3
RAMB18X2_RAMB18X2_LOWER
  • ADDRAL10=4
  • ADDRAL11=4
  • ADDRAL12=4
  • ADDRAL13=4
  • ADDRAL14=4
  • ADDRAL15=4
  • ADDRAL4=4
  • ADDRAL5=4
  • ADDRAL6=4
  • ADDRAL7=4
  • ADDRAL8=4
  • ADDRAL9=4
  • ADDRBL10=4
  • ADDRBL11=4
  • ADDRBL12=4
  • ADDRBL13=4
  • ADDRBL14=4
  • ADDRBL15=4
  • ADDRBL4=3
  • ADDRBL5=4
  • ADDRBL6=4
  • ADDRBL7=4
  • ADDRBL8=4
  • ADDRBL9=4
  • CLKAL=4
  • CLKBL=4
  • DIAL0=4
  • DIAL1=4
  • DIAL2=4
  • DIAL3=4
  • DIAL4=4
  • DIAL5=4
  • DIAL6=4
  • DIAL7=4
  • DIBL0=4
  • DIBL1=4
  • DIBL10=1
  • DIBL11=1
  • DIBL12=1
  • DIBL13=1
  • DIBL14=1
  • DIBL15=1
  • DIBL2=4
  • DIBL3=4
  • DIBL4=4
  • DIBL5=4
  • DIBL6=4
  • DIBL7=4
  • DIBL8=1
  • DIBL9=1
  • DIPAL0=4
  • DIPBL0=4
  • DIPBL1=1
  • DOBL0=4
  • DOBL1=4
  • DOBL10=1
  • DOBL11=1
  • DOBL12=1
  • DOBL13=1
  • DOBL14=1
  • DOBL15=1
  • DOBL2=4
  • DOBL3=4
  • DOBL4=4
  • DOBL5=4
  • DOBL6=4
  • DOBL7=4
  • DOBL8=1
  • DOBL9=1
  • DOPBL0=4
  • DOPBL1=1
  • ENAL=4
  • ENBL=4
  • REGCEAL=4
  • REGCEBL=4
  • REGCLKAL=4
  • REGCLKBL=4
  • SSRAL=4
  • SSRBL=4
  • WEAL0=4
  • WEAL1=4
  • WEAL2=4
  • WEAL3=4
  • WEBL0=4
  • WEBL1=4
  • WEBL2=4
  • WEBL3=4
  • WEBL4=4
  • WEBL5=4
  • WEBL6=4
  • WEBL7=4
RAMB18X2_RAMB18X2_UPPER
  • ADDRAU10=3
  • ADDRAU11=3
  • ADDRAU12=3
  • ADDRAU13=3
  • ADDRAU14=3
  • ADDRAU4=3
  • ADDRAU5=3
  • ADDRAU6=3
  • ADDRAU7=3
  • ADDRAU8=3
  • ADDRAU9=3
  • ADDRBU10=3
  • ADDRBU11=3
  • ADDRBU12=3
  • ADDRBU13=3
  • ADDRBU14=3
  • ADDRBU4=3
  • ADDRBU5=3
  • ADDRBU6=3
  • ADDRBU7=3
  • ADDRBU8=3
  • ADDRBU9=3
  • CLKAU=3
  • CLKBU=3
  • DIAU0=3
  • DIAU1=3
  • DIAU2=3
  • DIAU3=3
  • DIAU4=3
  • DIAU5=3
  • DIAU6=3
  • DIAU7=3
  • DIBU0=3
  • DIBU1=3
  • DIBU2=3
  • DIBU3=3
  • DIBU4=3
  • DIBU5=3
  • DIBU6=3
  • DIBU7=3
  • DIPAU0=3
  • DIPBU0=3
  • DOBU0=3
  • DOBU1=3
  • DOBU2=3
  • DOBU3=3
  • DOBU4=3
  • DOBU5=3
  • DOBU6=3
  • DOBU7=3
  • DOPBU0=3
  • ENAU=3
  • ENBU=3
  • REGCEAU=3
  • REGCEBU=3
  • REGCLKAU=3
  • REGCLKBU=3
  • SSRAU=3
  • SSRBU=3
  • WEAU0=3
  • WEAU1=3
  • WEAU2=3
  • WEAU3=3
  • WEBU0=3
  • WEBU1=3
  • WEBU2=3
  • WEBU3=3
  • WEBU4=3
  • WEBU5=3
  • WEBU6=3
  • WEBU7=3
RAMB36_EXP
  • ADDRAL10=32
  • ADDRAL11=32
  • ADDRAL12=32
  • ADDRAL13=32
  • ADDRAL14=32
  • ADDRAL15=32
  • ADDRAL3=32
  • ADDRAL4=32
  • ADDRAL5=32
  • ADDRAL6=32
  • ADDRAL7=32
  • ADDRAL8=32
  • ADDRAL9=32
  • ADDRAU10=32
  • ADDRAU11=32
  • ADDRAU12=32
  • ADDRAU13=32
  • ADDRAU14=32
  • ADDRAU3=32
  • ADDRAU4=32
  • ADDRAU5=32
  • ADDRAU6=32
  • ADDRAU7=32
  • ADDRAU8=32
  • ADDRAU9=32
  • ADDRBL10=32
  • ADDRBL11=32
  • ADDRBL12=32
  • ADDRBL13=32
  • ADDRBL14=32
  • ADDRBL15=32
  • ADDRBL3=32
  • ADDRBL4=32
  • ADDRBL5=32
  • ADDRBL6=32
  • ADDRBL7=32
  • ADDRBL8=32
  • ADDRBL9=32
  • ADDRBU10=32
  • ADDRBU11=32
  • ADDRBU12=32
  • ADDRBU13=32
  • ADDRBU14=32
  • ADDRBU3=32
  • ADDRBU4=32
  • ADDRBU5=32
  • ADDRBU6=32
  • ADDRBU7=32
  • ADDRBU8=32
  • ADDRBU9=32
  • CLKAL=32
  • CLKAU=32
  • CLKBL=32
  • CLKBU=32
  • DIA0=32
  • DIA1=32
  • DIA2=32
  • DIA3=32
  • DIA4=32
  • DIA5=32
  • DIA6=32
  • DIA7=32
  • DIB0=32
  • DIB1=32
  • DIB2=32
  • DIB3=32
  • DIB4=32
  • DIB5=32
  • DIB6=32
  • DIB7=32
  • DIPA0=32
  • DIPA1=32
  • DIPB0=32
  • DIPB1=32
  • DOB0=32
  • DOB1=32
  • DOB2=32
  • DOB3=32
  • DOB4=32
  • DOB5=32
  • DOB6=32
  • DOB7=32
  • DOPB0=32
  • ENAL=32
  • ENAU=32
  • ENBL=32
  • ENBU=32
  • REGCEAL=32
  • REGCEAU=32
  • REGCEBL=32
  • REGCEBU=32
  • REGCLKAL=32
  • REGCLKAU=32
  • REGCLKBL=32
  • REGCLKBU=32
  • SSRAL=32
  • SSRAU=32
  • SSRBL=32
  • SSRBU=32
  • WEAL0=32
  • WEAL1=32
  • WEAL2=32
  • WEAL3=32
  • WEAU0=32
  • WEAU1=32
  • WEAU2=32
  • WEAU3=32
  • WEBL0=32
  • WEBL1=32
  • WEBL2=32
  • WEBL3=32
  • WEBL4=32
  • WEBL5=32
  • WEBL6=32
  • WEBL7=32
  • WEBU0=32
  • WEBU1=32
  • WEBU2=32
  • WEBU3=32
  • WEBU4=32
  • WEBU5=32
  • WEBU6=32
  • WEBU7=32
RAMB36_EXP_RAMB36_EXP
  • ADDRAL10=32
  • ADDRAL11=32
  • ADDRAL12=32
  • ADDRAL13=32
  • ADDRAL14=32
  • ADDRAL15=32
  • ADDRAL3=32
  • ADDRAL4=32
  • ADDRAL5=32
  • ADDRAL6=32
  • ADDRAL7=32
  • ADDRAL8=32
  • ADDRAL9=32
  • ADDRAU10=32
  • ADDRAU11=32
  • ADDRAU12=32
  • ADDRAU13=32
  • ADDRAU14=32
  • ADDRAU3=32
  • ADDRAU4=32
  • ADDRAU5=32
  • ADDRAU6=32
  • ADDRAU7=32
  • ADDRAU8=32
  • ADDRAU9=32
  • ADDRBL10=32
  • ADDRBL11=32
  • ADDRBL12=32
  • ADDRBL13=32
  • ADDRBL14=32
  • ADDRBL15=32
  • ADDRBL3=32
  • ADDRBL4=32
  • ADDRBL5=32
  • ADDRBL6=32
  • ADDRBL7=32
  • ADDRBL8=32
  • ADDRBL9=32
  • ADDRBU10=32
  • ADDRBU11=32
  • ADDRBU12=32
  • ADDRBU13=32
  • ADDRBU14=32
  • ADDRBU3=32
  • ADDRBU4=32
  • ADDRBU5=32
  • ADDRBU6=32
  • ADDRBU7=32
  • ADDRBU8=32
  • ADDRBU9=32
  • CLKAL=32
  • CLKAU=32
  • CLKBL=32
  • CLKBU=32
  • DIA0=32
  • DIA1=32
  • DIA2=32
  • DIA3=32
  • DIA4=32
  • DIA5=32
  • DIA6=32
  • DIA7=32
  • DIB0=32
  • DIB1=32
  • DIB2=32
  • DIB3=32
  • DIB4=32
  • DIB5=32
  • DIB6=32
  • DIB7=32
  • DIPA0=32
  • DIPA1=32
  • DIPB0=32
  • DIPB1=32
  • DOB0=32
  • DOB1=32
  • DOB2=32
  • DOB3=32
  • DOB4=32
  • DOB5=32
  • DOB6=32
  • DOB7=32
  • DOPB0=32
  • ENAL=32
  • ENAU=32
  • ENBL=32
  • ENBU=32
  • REGCEAL=32
  • REGCEAU=32
  • REGCEBL=32
  • REGCEBU=32
  • REGCLKAL=32
  • REGCLKAU=32
  • REGCLKBL=32
  • REGCLKBU=32
  • SSRAL=32
  • SSRAU=32
  • SSRBL=32
  • SSRBU=32
  • WEAL0=32
  • WEAL1=32
  • WEAL2=32
  • WEAL3=32
  • WEAU0=32
  • WEAU1=32
  • WEAU2=32
  • WEAU3=32
  • WEBL0=32
  • WEBL1=32
  • WEBL2=32
  • WEBL3=32
  • WEBL4=32
  • WEBL5=32
  • WEBL6=32
  • WEBL7=32
  • WEBU0=32
  • WEBU1=32
  • WEBU2=32
  • WEBU3=32
  • WEBU4=32
  • WEBU5=32
  • WEBU6=32
  • WEBU7=32
SLICEL
  • A=210
  • A1=150
  • A2=222
  • A3=293
  • A4=390
  • A5=411
  • A6=453
  • AMUX=8
  • AQ=388
  • AX=239
  • B=124
  • B1=93
  • B2=128
  • B3=168
  • B4=253
  • B5=270
  • B6=302
  • BMUX=7
  • BQ=289
  • BX=181
  • C=72
  • C1=102
  • C2=137
  • C3=168
  • C4=229
  • C5=236
  • C6=266
  • CE=270
  • CIN=79
  • CLK=506
  • CMUX=11
  • COUT=79
  • CQ=279
  • CX=183
  • D=145
  • D1=99
  • D2=145
  • D3=202
  • D4=281
  • D5=297
  • D6=331
  • DMUX=3
  • DQ=298
  • DX=175
  • SR=107
SLICEL_A5LUT
  • A3=2
  • A4=8
  • O5=71
SLICEL_A6LUT
  • A1=150
  • A2=222
  • A3=293
  • A4=388
  • A5=411
  • A6=453
  • O6=458
SLICEL_AFF
  • CE=211
  • CK=388
  • D=388
  • Q=388
  • REV=5
  • SR=75
SLICEL_B5LUT
  • A1=2
  • A2=4
  • A3=4
  • A4=4
  • O5=61
SLICEL_B6LUT
  • A1=93
  • A2=128
  • A3=168
  • A4=253
  • A5=270
  • A6=302
  • O6=304
SLICEL_BFF
  • CE=185
  • CK=289
  • D=289
  • Q=289
  • REV=3
  • SR=42
SLICEL_C5LUT
  • O5=55
SLICEL_C6LUT
  • A1=102
  • A2=137
  • A3=168
  • A4=229
  • A5=236
  • A6=266
  • O6=269
SLICEL_CARRY4
  • CIN=79
  • CO3=79
  • CYINIT=32
  • DI0=101
  • DI1=97
  • DI2=96
  • DI3=79
  • O0=103
  • O1=95
  • O2=95
  • O3=95
  • S0=111
  • S1=101
  • S2=97
  • S3=96
SLICEL_CFF
  • CE=166
  • CK=279
  • D=279
  • Q=279
  • REV=2
  • SR=38
SLICEL_CYINITGND
  • 0=9
SLICEL_CYINITVCC
  • 1=9
SLICEL_D5LUT
  • O5=46
SLICEL_D6LUT
  • A1=99
  • A2=145
  • A3=202
  • A4=281
  • A5=297
  • A6=331
  • O6=340
SLICEL_DFF
  • CE=177
  • CK=298
  • D=298
  • Q=298
  • REV=2
  • SR=49
SLICEL_F7AMUX
  • 0=23
  • 1=23
  • OUT=23
  • S0=23
SLICEL_F7BMUX
  • 0=30
  • 1=30
  • OUT=30
  • S0=30
SLICEL_F8MUX
  • 0=18
  • 1=18
  • OUT=18
  • S0=18
SLICEM
  • A=2
  • A1=22
  • A2=22
  • A3=22
  • A4=22
  • A5=22
  • A6=22
  • AI=18
  • AMUX=2
  • AQ=20
  • AX=4
  • B=2
  • B1=13
  • B2=13
  • B3=13
  • B4=13
  • B5=13
  • B6=13
  • BI=9
  • BMUX=2
  • BQ=11
  • BX=6
  • C=2
  • C1=9
  • C2=9
  • C3=9
  • C4=9
  • C5=9
  • C6=9
  • CE=24
  • CI=4
  • CLK=24
  • CMUX=2
  • CQ=7
  • CX=5
  • D=3
  • D1=8
  • D2=9
  • D3=9
  • D4=9
  • D5=9
  • D6=9
  • DI=3
  • DMUX=2
  • DQ=6
  • DX=7
SLICEM_A5LUT
  • A1=2
  • A2=2
  • A3=2
  • A4=2
  • A5=2
  • CLK=2
  • DI1=2
  • O5=2
  • WA1=2
  • WA2=2
  • WA3=2
  • WA4=2
  • WA5=2
  • WE=2
SLICEM_A6LUT
  • A1=22
  • A2=22
  • A3=22
  • A4=22
  • A5=22
  • A6=22
  • CLK=22
  • DI1=4
  • DI2=18
  • O6=22
  • WA1=6
  • WA2=6
  • WA3=6
  • WA4=6
  • WA5=6
  • WA6=6
  • WE=22
SLICEM_AFF
  • CE=3
  • CK=20
  • D=20
  • Q=20
SLICEM_B5LUT
  • A1=2
  • A2=2
  • A3=2
  • A4=2
  • A5=2
  • CLK=2
  • DI1=2
  • O5=2
  • WA1=2
  • WA2=2
  • WA3=2
  • WA4=2
  • WA5=2
  • WE=2
SLICEM_B6LUT
  • A1=13
  • A2=13
  • A3=13
  • A4=13
  • A5=13
  • A6=13
  • CLK=13
  • DI1=4
  • DI2=9
  • O6=13
  • WA1=6
  • WA2=6
  • WA3=6
  • WA4=6
  • WA5=6
  • WA6=6
  • WE=13
SLICEM_BFF
  • CK=11
  • D=11
  • Q=11
SLICEM_C5LUT
  • A1=2
  • A2=2
  • A3=2
  • A4=2
  • A5=2
  • CLK=2
  • DI1=2
  • O5=2
  • WA1=2
  • WA2=2
  • WA3=2
  • WA4=2
  • WA5=2
  • WE=2
SLICEM_C6LUT
  • A1=9
  • A2=9
  • A3=9
  • A4=9
  • A5=9
  • A6=9
  • CLK=9
  • DI1=5
  • DI2=4
  • O6=9
  • WA1=7
  • WA2=7
  • WA3=7
  • WA4=7
  • WA5=7
  • WA6=7
  • WE=9
SLICEM_CARRY4
  • CO3=26
  • CYINIT=26
  • DI0=26
  • DI1=26
  • DI2=26
  • DI3=26
  • S0=26
  • S1=26
  • S2=26
  • S3=26
SLICEM_CFF
  • CK=7
  • D=7
  • Q=7
SLICEM_CYINITVCC
  • 1=26
SLICEM_D5LUT
  • A1=2
  • A2=2
  • A3=2
  • A4=2
  • A5=2
  • CLK=2
  • DI1=2
  • O5=2
  • WA1=2
  • WA2=2
  • WA3=2
  • WA4=2
  • WA5=2
  • WE=2
SLICEM_D6LUT
  • A1=8
  • A2=9
  • A3=9
  • A4=9
  • A5=9
  • A6=9
  • CLK=8
  • DI1=5
  • DI2=3
  • O6=9
  • WA1=7
  • WA2=7
  • WA3=7
  • WA4=7
  • WA5=7
  • WA6=7
  • WE=8
SLICEM_DFF
  • CK=6
  • D=6
  • Q=6
SLICEM_F7AMUX
  • 0=5
  • 1=5
  • OUT=5
  • S0=5
SLICEM_F7BMUX
  • 0=2
  • 1=2
  • OUT=2
  • S0=2
SLICEM_F8MUX
  • 0=2
  • 1=2
  • OUT=2
  • S0=2
TEMAC
  • CLIENTEMAC0DCMLOCKED=2
  • CLIENTEMAC0PAUSEREQ=2
  • CLIENTEMAC0PAUSEVAL0=2
  • CLIENTEMAC0PAUSEVAL1=2
  • CLIENTEMAC0PAUSEVAL10=2
  • CLIENTEMAC0PAUSEVAL11=2
  • CLIENTEMAC0PAUSEVAL12=2
  • CLIENTEMAC0PAUSEVAL13=2
  • CLIENTEMAC0PAUSEVAL14=2
  • CLIENTEMAC0PAUSEVAL15=2
  • CLIENTEMAC0PAUSEVAL2=2
  • CLIENTEMAC0PAUSEVAL3=2
  • CLIENTEMAC0PAUSEVAL4=2
  • CLIENTEMAC0PAUSEVAL5=2
  • CLIENTEMAC0PAUSEVAL6=2
  • CLIENTEMAC0PAUSEVAL7=2
  • CLIENTEMAC0PAUSEVAL8=2
  • CLIENTEMAC0PAUSEVAL9=2
  • CLIENTEMAC0RXCLIENTCLKIN=2
  • CLIENTEMAC0TXCLIENTCLKIN=2
  • CLIENTEMAC0TXD0=2
  • CLIENTEMAC0TXD1=2
  • CLIENTEMAC0TXD10=2
  • CLIENTEMAC0TXD11=2
  • CLIENTEMAC0TXD12=2
  • CLIENTEMAC0TXD13=2
  • CLIENTEMAC0TXD14=2
  • CLIENTEMAC0TXD15=2
  • CLIENTEMAC0TXD2=2
  • CLIENTEMAC0TXD3=2
  • CLIENTEMAC0TXD4=2
  • CLIENTEMAC0TXD5=2
  • CLIENTEMAC0TXD6=2
  • CLIENTEMAC0TXD7=2
  • CLIENTEMAC0TXD8=2
  • CLIENTEMAC0TXD9=2
  • CLIENTEMAC0TXDVLD=2
  • CLIENTEMAC0TXDVLDMSW=2
  • CLIENTEMAC0TXFIRSTBYTE=2
  • CLIENTEMAC0TXIFGDELAY0=2
  • CLIENTEMAC0TXIFGDELAY1=2
  • CLIENTEMAC0TXIFGDELAY2=2
  • CLIENTEMAC0TXIFGDELAY3=2
  • CLIENTEMAC0TXIFGDELAY4=2
  • CLIENTEMAC0TXIFGDELAY5=2
  • CLIENTEMAC0TXIFGDELAY6=2
  • CLIENTEMAC0TXIFGDELAY7=2
  • CLIENTEMAC0TXUNDERRUN=2
  • CLIENTEMAC1DCMLOCKED=2
  • CLIENTEMAC1PAUSEREQ=2
  • CLIENTEMAC1PAUSEVAL0=2
  • CLIENTEMAC1PAUSEVAL1=2
  • CLIENTEMAC1PAUSEVAL10=2
  • CLIENTEMAC1PAUSEVAL11=2
  • CLIENTEMAC1PAUSEVAL12=2
  • CLIENTEMAC1PAUSEVAL13=2
  • CLIENTEMAC1PAUSEVAL14=2
  • CLIENTEMAC1PAUSEVAL15=2
  • CLIENTEMAC1PAUSEVAL2=2
  • CLIENTEMAC1PAUSEVAL3=2
  • CLIENTEMAC1PAUSEVAL4=2
  • CLIENTEMAC1PAUSEVAL5=2
  • CLIENTEMAC1PAUSEVAL6=2
  • CLIENTEMAC1PAUSEVAL7=2
  • CLIENTEMAC1PAUSEVAL8=2
  • CLIENTEMAC1PAUSEVAL9=2
  • CLIENTEMAC1RXCLIENTCLKIN=2
  • CLIENTEMAC1TXCLIENTCLKIN=2
  • CLIENTEMAC1TXD0=2
  • CLIENTEMAC1TXD1=2
  • CLIENTEMAC1TXD10=2
  • CLIENTEMAC1TXD11=2
  • CLIENTEMAC1TXD12=2
  • CLIENTEMAC1TXD13=2
  • CLIENTEMAC1TXD14=2
  • CLIENTEMAC1TXD15=2
  • CLIENTEMAC1TXD2=2
  • CLIENTEMAC1TXD3=2
  • CLIENTEMAC1TXD4=2
  • CLIENTEMAC1TXD5=2
  • CLIENTEMAC1TXD6=2
  • CLIENTEMAC1TXD7=2
  • CLIENTEMAC1TXD8=2
  • CLIENTEMAC1TXD9=2
  • CLIENTEMAC1TXDVLD=2
  • CLIENTEMAC1TXDVLDMSW=2
  • CLIENTEMAC1TXFIRSTBYTE=2
  • CLIENTEMAC1TXIFGDELAY0=2
  • CLIENTEMAC1TXIFGDELAY1=2
  • CLIENTEMAC1TXIFGDELAY2=2
  • CLIENTEMAC1TXIFGDELAY3=2
  • CLIENTEMAC1TXIFGDELAY4=2
  • CLIENTEMAC1TXIFGDELAY5=2
  • CLIENTEMAC1TXIFGDELAY6=2
  • CLIENTEMAC1TXIFGDELAY7=2
  • CLIENTEMAC1TXUNDERRUN=2
  • DCREMACABUS0=2
  • DCREMACABUS1=2
  • DCREMACABUS2=2
  • DCREMACABUS3=2
  • DCREMACABUS4=2
  • DCREMACABUS5=2
  • DCREMACABUS6=2
  • DCREMACABUS7=2
  • DCREMACABUS8=2
  • DCREMACABUS9=2
  • DCREMACCLK=2
  • DCREMACDBUS0=2
  • DCREMACDBUS1=2
  • DCREMACDBUS10=2
  • DCREMACDBUS11=2
  • DCREMACDBUS12=2
  • DCREMACDBUS13=2
  • DCREMACDBUS14=2
  • DCREMACDBUS15=2
  • DCREMACDBUS16=2
  • DCREMACDBUS17=2
  • DCREMACDBUS18=2
  • DCREMACDBUS19=2
  • DCREMACDBUS2=2
  • DCREMACDBUS20=2
  • DCREMACDBUS21=2
  • DCREMACDBUS22=2
  • DCREMACDBUS23=2
  • DCREMACDBUS24=2
  • DCREMACDBUS25=2
  • DCREMACDBUS26=2
  • DCREMACDBUS27=2
  • DCREMACDBUS28=2
  • DCREMACDBUS29=2
  • DCREMACDBUS3=2
  • DCREMACDBUS30=2
  • DCREMACDBUS31=2
  • DCREMACDBUS4=2
  • DCREMACDBUS5=2
  • DCREMACDBUS6=2
  • DCREMACDBUS7=2
  • DCREMACDBUS8=2
  • DCREMACDBUS9=2
  • DCREMACENABLE=2
  • DCREMACREAD=2
  • DCREMACWRITE=2
  • EMAC0CLIENTANINTERRUPT=2
  • EMAC0CLIENTRXBADFRAME=2
  • EMAC0CLIENTRXD0=2
  • EMAC0CLIENTRXD1=2
  • EMAC0CLIENTRXD2=2
  • EMAC0CLIENTRXD3=2
  • EMAC0CLIENTRXD4=2
  • EMAC0CLIENTRXD5=2
  • EMAC0CLIENTRXD6=2
  • EMAC0CLIENTRXD7=2
  • EMAC0CLIENTRXDVLD=2
  • EMAC0CLIENTRXGOODFRAME=2
  • EMAC0CLIENTTXACK=2
  • EMAC0CLIENTTXCLIENTCLKOUT=2
  • EMAC0CLIENTTXCOLLISION=2
  • EMAC0CLIENTTXRETRANSMIT=2
  • EMAC0PHYENCOMMAALIGN=2
  • EMAC0PHYLOOPBACKMSB=2
  • EMAC0PHYMCLKOUT=1
  • EMAC0PHYMDOUT=1
  • EMAC0PHYMDTRI=1
  • EMAC0PHYMGTRXRESET=2
  • EMAC0PHYMGTTXRESET=2
  • EMAC0PHYPOWERDOWN=2
  • EMAC0PHYSYNCACQSTATUS=2
  • EMAC0PHYTXCHARDISPMODE=2
  • EMAC0PHYTXCHARDISPVAL=2
  • EMAC0PHYTXCHARISK=2
  • EMAC0PHYTXD0=2
  • EMAC0PHYTXD1=2
  • EMAC0PHYTXD2=2
  • EMAC0PHYTXD3=2
  • EMAC0PHYTXD4=2
  • EMAC0PHYTXD5=2
  • EMAC0PHYTXD6=2
  • EMAC0PHYTXD7=2
  • HOSTADDR0=2
  • HOSTADDR1=2
  • HOSTADDR2=2
  • HOSTADDR3=2
  • HOSTADDR4=2
  • HOSTADDR5=2
  • HOSTADDR6=2
  • HOSTADDR7=2
  • HOSTADDR8=2
  • HOSTADDR9=2
  • HOSTCLK=2
  • HOSTEMAC1SEL=2
  • HOSTMIIMRDY=2
  • HOSTMIIMSEL=2
  • HOSTOPCODE0=2
  • HOSTOPCODE1=2
  • HOSTRDDATA0=2
  • HOSTRDDATA1=2
  • HOSTRDDATA10=2
  • HOSTRDDATA11=2
  • HOSTRDDATA12=2
  • HOSTRDDATA13=2
  • HOSTRDDATA14=2
  • HOSTRDDATA15=2
  • HOSTRDDATA16=2
  • HOSTRDDATA17=2
  • HOSTRDDATA18=2
  • HOSTRDDATA19=2
  • HOSTRDDATA2=2
  • HOSTRDDATA20=2
  • HOSTRDDATA21=2
  • HOSTRDDATA22=2
  • HOSTRDDATA23=2
  • HOSTRDDATA24=2
  • HOSTRDDATA25=2
  • HOSTRDDATA26=2
  • HOSTRDDATA27=2
  • HOSTRDDATA28=2
  • HOSTRDDATA29=2
  • HOSTRDDATA3=2
  • HOSTRDDATA30=2
  • HOSTRDDATA31=2
  • HOSTRDDATA4=2
  • HOSTRDDATA5=2
  • HOSTRDDATA6=2
  • HOSTRDDATA7=2
  • HOSTRDDATA8=2
  • HOSTRDDATA9=2
  • HOSTREQ=2
  • HOSTWRDATA0=2
  • HOSTWRDATA1=2
  • HOSTWRDATA10=2
  • HOSTWRDATA11=2
  • HOSTWRDATA12=2
  • HOSTWRDATA13=2
  • HOSTWRDATA14=2
  • HOSTWRDATA15=2
  • HOSTWRDATA16=2
  • HOSTWRDATA17=2
  • HOSTWRDATA18=2
  • HOSTWRDATA19=2
  • HOSTWRDATA2=2
  • HOSTWRDATA20=2
  • HOSTWRDATA21=2
  • HOSTWRDATA22=2
  • HOSTWRDATA23=2
  • HOSTWRDATA24=2
  • HOSTWRDATA25=2
  • HOSTWRDATA26=2
  • HOSTWRDATA27=2
  • HOSTWRDATA28=2
  • HOSTWRDATA29=2
  • HOSTWRDATA3=2
  • HOSTWRDATA30=2
  • HOSTWRDATA31=2
  • HOSTWRDATA4=2
  • HOSTWRDATA5=2
  • HOSTWRDATA6=2
  • HOSTWRDATA7=2
  • HOSTWRDATA8=2
  • HOSTWRDATA9=2
  • PHYEMAC0COL=2
  • PHYEMAC0CRS=2
  • PHYEMAC0GTXCLK=2
  • PHYEMAC0MCLKIN=2
  • PHYEMAC0MDIN=2
  • PHYEMAC0MIITXCLK=2
  • PHYEMAC0PHYAD0=2
  • PHYEMAC0PHYAD1=2
  • PHYEMAC0PHYAD2=2
  • PHYEMAC0PHYAD3=2
  • PHYEMAC0PHYAD4=2
  • PHYEMAC0RXBUFERR=2
  • PHYEMAC0RXBUFSTATUS0=2
  • PHYEMAC0RXBUFSTATUS1=2
  • PHYEMAC0RXCHARISCOMMA=2
  • PHYEMAC0RXCHARISK=2
  • PHYEMAC0RXCHECKINGCRC=2
  • PHYEMAC0RXCLK=2
  • PHYEMAC0RXCLKCORCNT0=2
  • PHYEMAC0RXCLKCORCNT1=2
  • PHYEMAC0RXCLKCORCNT2=2
  • PHYEMAC0RXCOMMADET=2
  • PHYEMAC0RXD0=2
  • PHYEMAC0RXD1=2
  • PHYEMAC0RXD2=2
  • PHYEMAC0RXD3=2
  • PHYEMAC0RXD4=2
  • PHYEMAC0RXD5=2
  • PHYEMAC0RXD6=2
  • PHYEMAC0RXD7=2
  • PHYEMAC0RXDISPERR=2
  • PHYEMAC0RXDV=2
  • PHYEMAC0RXER=2
  • PHYEMAC0RXLOSSOFSYNC0=2
  • PHYEMAC0RXLOSSOFSYNC1=2
  • PHYEMAC0RXNOTINTABLE=2
  • PHYEMAC0RXRUNDISP=2
  • PHYEMAC0SIGNALDET=2
  • PHYEMAC0TXBUFERR=2
  • PHYEMAC0TXGMIIMIICLKIN=2
  • PHYEMAC1COL=2
  • PHYEMAC1CRS=2
  • PHYEMAC1GTXCLK=2
  • PHYEMAC1MCLKIN=2
  • PHYEMAC1MDIN=2
  • PHYEMAC1MIITXCLK=2
  • PHYEMAC1PHYAD0=2
  • PHYEMAC1PHYAD1=2
  • PHYEMAC1PHYAD2=2
  • PHYEMAC1PHYAD3=2
  • PHYEMAC1PHYAD4=2
  • PHYEMAC1RXBUFERR=2
  • PHYEMAC1RXBUFSTATUS0=2
  • PHYEMAC1RXBUFSTATUS1=2
  • PHYEMAC1RXCHARISCOMMA=2
  • PHYEMAC1RXCHARISK=2
  • PHYEMAC1RXCHECKINGCRC=2
  • PHYEMAC1RXCLK=2
  • PHYEMAC1RXCLKCORCNT0=2
  • PHYEMAC1RXCLKCORCNT1=2
  • PHYEMAC1RXCLKCORCNT2=2
  • PHYEMAC1RXCOMMADET=2
  • PHYEMAC1RXD0=2
  • PHYEMAC1RXD1=2
  • PHYEMAC1RXD2=2
  • PHYEMAC1RXD3=2
  • PHYEMAC1RXD4=2
  • PHYEMAC1RXD5=2
  • PHYEMAC1RXD6=2
  • PHYEMAC1RXD7=2
  • PHYEMAC1RXDISPERR=2
  • PHYEMAC1RXDV=2
  • PHYEMAC1RXER=2
  • PHYEMAC1RXLOSSOFSYNC0=2
  • PHYEMAC1RXLOSSOFSYNC1=2
  • PHYEMAC1RXNOTINTABLE=2
  • PHYEMAC1RXRUNDISP=2
  • PHYEMAC1SIGNALDET=2
  • PHYEMAC1TXBUFERR=2
  • PHYEMAC1TXGMIIMIICLKIN=2
  • RESET=2
TEMAC_TEMAC
  • CLIENTEMAC0DCMLOCKED=2
  • CLIENTEMAC0PAUSEREQ=2
  • CLIENTEMAC0PAUSEVAL0=2
  • CLIENTEMAC0PAUSEVAL1=2
  • CLIENTEMAC0PAUSEVAL10=2
  • CLIENTEMAC0PAUSEVAL11=2
  • CLIENTEMAC0PAUSEVAL12=2
  • CLIENTEMAC0PAUSEVAL13=2
  • CLIENTEMAC0PAUSEVAL14=2
  • CLIENTEMAC0PAUSEVAL15=2
  • CLIENTEMAC0PAUSEVAL2=2
  • CLIENTEMAC0PAUSEVAL3=2
  • CLIENTEMAC0PAUSEVAL4=2
  • CLIENTEMAC0PAUSEVAL5=2
  • CLIENTEMAC0PAUSEVAL6=2
  • CLIENTEMAC0PAUSEVAL7=2
  • CLIENTEMAC0PAUSEVAL8=2
  • CLIENTEMAC0PAUSEVAL9=2
  • CLIENTEMAC0RXCLIENTCLKIN=2
  • CLIENTEMAC0TXCLIENTCLKIN=2
  • CLIENTEMAC0TXD0=2
  • CLIENTEMAC0TXD1=2
  • CLIENTEMAC0TXD10=2
  • CLIENTEMAC0TXD11=2
  • CLIENTEMAC0TXD12=2
  • CLIENTEMAC0TXD13=2
  • CLIENTEMAC0TXD14=2
  • CLIENTEMAC0TXD15=2
  • CLIENTEMAC0TXD2=2
  • CLIENTEMAC0TXD3=2
  • CLIENTEMAC0TXD4=2
  • CLIENTEMAC0TXD5=2
  • CLIENTEMAC0TXD6=2
  • CLIENTEMAC0TXD7=2
  • CLIENTEMAC0TXD8=2
  • CLIENTEMAC0TXD9=2
  • CLIENTEMAC0TXDVLD=2
  • CLIENTEMAC0TXDVLDMSW=2
  • CLIENTEMAC0TXFIRSTBYTE=2
  • CLIENTEMAC0TXIFGDELAY0=2
  • CLIENTEMAC0TXIFGDELAY1=2
  • CLIENTEMAC0TXIFGDELAY2=2
  • CLIENTEMAC0TXIFGDELAY3=2
  • CLIENTEMAC0TXIFGDELAY4=2
  • CLIENTEMAC0TXIFGDELAY5=2
  • CLIENTEMAC0TXIFGDELAY6=2
  • CLIENTEMAC0TXIFGDELAY7=2
  • CLIENTEMAC0TXUNDERRUN=2
  • CLIENTEMAC1DCMLOCKED=2
  • CLIENTEMAC1PAUSEREQ=2
  • CLIENTEMAC1PAUSEVAL0=2
  • CLIENTEMAC1PAUSEVAL1=2
  • CLIENTEMAC1PAUSEVAL10=2
  • CLIENTEMAC1PAUSEVAL11=2
  • CLIENTEMAC1PAUSEVAL12=2
  • CLIENTEMAC1PAUSEVAL13=2
  • CLIENTEMAC1PAUSEVAL14=2
  • CLIENTEMAC1PAUSEVAL15=2
  • CLIENTEMAC1PAUSEVAL2=2
  • CLIENTEMAC1PAUSEVAL3=2
  • CLIENTEMAC1PAUSEVAL4=2
  • CLIENTEMAC1PAUSEVAL5=2
  • CLIENTEMAC1PAUSEVAL6=2
  • CLIENTEMAC1PAUSEVAL7=2
  • CLIENTEMAC1PAUSEVAL8=2
  • CLIENTEMAC1PAUSEVAL9=2
  • CLIENTEMAC1RXCLIENTCLKIN=2
  • CLIENTEMAC1TXCLIENTCLKIN=2
  • CLIENTEMAC1TXD0=2
  • CLIENTEMAC1TXD1=2
  • CLIENTEMAC1TXD10=2
  • CLIENTEMAC1TXD11=2
  • CLIENTEMAC1TXD12=2
  • CLIENTEMAC1TXD13=2
  • CLIENTEMAC1TXD14=2
  • CLIENTEMAC1TXD15=2
  • CLIENTEMAC1TXD2=2
  • CLIENTEMAC1TXD3=2
  • CLIENTEMAC1TXD4=2
  • CLIENTEMAC1TXD5=2
  • CLIENTEMAC1TXD6=2
  • CLIENTEMAC1TXD7=2
  • CLIENTEMAC1TXD8=2
  • CLIENTEMAC1TXD9=2
  • CLIENTEMAC1TXDVLD=2
  • CLIENTEMAC1TXDVLDMSW=2
  • CLIENTEMAC1TXFIRSTBYTE=2
  • CLIENTEMAC1TXIFGDELAY0=2
  • CLIENTEMAC1TXIFGDELAY1=2
  • CLIENTEMAC1TXIFGDELAY2=2
  • CLIENTEMAC1TXIFGDELAY3=2
  • CLIENTEMAC1TXIFGDELAY4=2
  • CLIENTEMAC1TXIFGDELAY5=2
  • CLIENTEMAC1TXIFGDELAY6=2
  • CLIENTEMAC1TXIFGDELAY7=2
  • CLIENTEMAC1TXUNDERRUN=2
  • DCREMACABUS0=2
  • DCREMACABUS1=2
  • DCREMACABUS2=2
  • DCREMACABUS3=2
  • DCREMACABUS4=2
  • DCREMACABUS5=2
  • DCREMACABUS6=2
  • DCREMACABUS7=2
  • DCREMACABUS8=2
  • DCREMACABUS9=2
  • DCREMACCLK=2
  • DCREMACDBUS0=2
  • DCREMACDBUS1=2
  • DCREMACDBUS10=2
  • DCREMACDBUS11=2
  • DCREMACDBUS12=2
  • DCREMACDBUS13=2
  • DCREMACDBUS14=2
  • DCREMACDBUS15=2
  • DCREMACDBUS16=2
  • DCREMACDBUS17=2
  • DCREMACDBUS18=2
  • DCREMACDBUS19=2
  • DCREMACDBUS2=2
  • DCREMACDBUS20=2
  • DCREMACDBUS21=2
  • DCREMACDBUS22=2
  • DCREMACDBUS23=2
  • DCREMACDBUS24=2
  • DCREMACDBUS25=2
  • DCREMACDBUS26=2
  • DCREMACDBUS27=2
  • DCREMACDBUS28=2
  • DCREMACDBUS29=2
  • DCREMACDBUS3=2
  • DCREMACDBUS30=2
  • DCREMACDBUS31=2
  • DCREMACDBUS4=2
  • DCREMACDBUS5=2
  • DCREMACDBUS6=2
  • DCREMACDBUS7=2
  • DCREMACDBUS8=2
  • DCREMACDBUS9=2
  • DCREMACENABLE=2
  • DCREMACREAD=2
  • DCREMACWRITE=2
  • EMAC0CLIENTANINTERRUPT=2
  • EMAC0CLIENTRXBADFRAME=2
  • EMAC0CLIENTRXD0=2
  • EMAC0CLIENTRXD1=2
  • EMAC0CLIENTRXD2=2
  • EMAC0CLIENTRXD3=2
  • EMAC0CLIENTRXD4=2
  • EMAC0CLIENTRXD5=2
  • EMAC0CLIENTRXD6=2
  • EMAC0CLIENTRXD7=2
  • EMAC0CLIENTRXDVLD=2
  • EMAC0CLIENTRXGOODFRAME=2
  • EMAC0CLIENTTXACK=2
  • EMAC0CLIENTTXCLIENTCLKOUT=2
  • EMAC0CLIENTTXCOLLISION=2
  • EMAC0CLIENTTXRETRANSMIT=2
  • EMAC0PHYENCOMMAALIGN=2
  • EMAC0PHYLOOPBACKMSB=2
  • EMAC0PHYMCLKOUT=1
  • EMAC0PHYMDOUT=1
  • EMAC0PHYMDTRI=1
  • EMAC0PHYMGTRXRESET=2
  • EMAC0PHYMGTTXRESET=2
  • EMAC0PHYPOWERDOWN=2
  • EMAC0PHYSYNCACQSTATUS=2
  • EMAC0PHYTXCHARDISPMODE=2
  • EMAC0PHYTXCHARDISPVAL=2
  • EMAC0PHYTXCHARISK=2
  • EMAC0PHYTXD0=2
  • EMAC0PHYTXD1=2
  • EMAC0PHYTXD2=2
  • EMAC0PHYTXD3=2
  • EMAC0PHYTXD4=2
  • EMAC0PHYTXD5=2
  • EMAC0PHYTXD6=2
  • EMAC0PHYTXD7=2
  • HOSTADDR0=2
  • HOSTADDR1=2
  • HOSTADDR2=2
  • HOSTADDR3=2
  • HOSTADDR4=2
  • HOSTADDR5=2
  • HOSTADDR6=2
  • HOSTADDR7=2
  • HOSTADDR8=2
  • HOSTADDR9=2
  • HOSTCLK=2
  • HOSTEMAC1SEL=2
  • HOSTMIIMRDY=2
  • HOSTMIIMSEL=2
  • HOSTOPCODE0=2
  • HOSTOPCODE1=2
  • HOSTRDDATA0=2
  • HOSTRDDATA1=2
  • HOSTRDDATA10=2
  • HOSTRDDATA11=2
  • HOSTRDDATA12=2
  • HOSTRDDATA13=2
  • HOSTRDDATA14=2
  • HOSTRDDATA15=2
  • HOSTRDDATA16=2
  • HOSTRDDATA17=2
  • HOSTRDDATA18=2
  • HOSTRDDATA19=2
  • HOSTRDDATA2=2
  • HOSTRDDATA20=2
  • HOSTRDDATA21=2
  • HOSTRDDATA22=2
  • HOSTRDDATA23=2
  • HOSTRDDATA24=2
  • HOSTRDDATA25=2
  • HOSTRDDATA26=2
  • HOSTRDDATA27=2
  • HOSTRDDATA28=2
  • HOSTRDDATA29=2
  • HOSTRDDATA3=2
  • HOSTRDDATA30=2
  • HOSTRDDATA31=2
  • HOSTRDDATA4=2
  • HOSTRDDATA5=2
  • HOSTRDDATA6=2
  • HOSTRDDATA7=2
  • HOSTRDDATA8=2
  • HOSTRDDATA9=2
  • HOSTREQ=2
  • HOSTWRDATA0=2
  • HOSTWRDATA1=2
  • HOSTWRDATA10=2
  • HOSTWRDATA11=2
  • HOSTWRDATA12=2
  • HOSTWRDATA13=2
  • HOSTWRDATA14=2
  • HOSTWRDATA15=2
  • HOSTWRDATA16=2
  • HOSTWRDATA17=2
  • HOSTWRDATA18=2
  • HOSTWRDATA19=2
  • HOSTWRDATA2=2
  • HOSTWRDATA20=2
  • HOSTWRDATA21=2
  • HOSTWRDATA22=2
  • HOSTWRDATA23=2
  • HOSTWRDATA24=2
  • HOSTWRDATA25=2
  • HOSTWRDATA26=2
  • HOSTWRDATA27=2
  • HOSTWRDATA28=2
  • HOSTWRDATA29=2
  • HOSTWRDATA3=2
  • HOSTWRDATA30=2
  • HOSTWRDATA31=2
  • HOSTWRDATA4=2
  • HOSTWRDATA5=2
  • HOSTWRDATA6=2
  • HOSTWRDATA7=2
  • HOSTWRDATA8=2
  • HOSTWRDATA9=2
  • PHYEMAC0COL=2
  • PHYEMAC0CRS=2
  • PHYEMAC0GTXCLK=2
  • PHYEMAC0MCLKIN=2
  • PHYEMAC0MDIN=2
  • PHYEMAC0MIITXCLK=2
  • PHYEMAC0PHYAD0=2
  • PHYEMAC0PHYAD1=2
  • PHYEMAC0PHYAD2=2
  • PHYEMAC0PHYAD3=2
  • PHYEMAC0PHYAD4=2
  • PHYEMAC0RXBUFERR=2
  • PHYEMAC0RXBUFSTATUS0=2
  • PHYEMAC0RXBUFSTATUS1=2
  • PHYEMAC0RXCHARISCOMMA=2
  • PHYEMAC0RXCHARISK=2
  • PHYEMAC0RXCHECKINGCRC=2
  • PHYEMAC0RXCLK=2
  • PHYEMAC0RXCLKCORCNT0=2
  • PHYEMAC0RXCLKCORCNT1=2
  • PHYEMAC0RXCLKCORCNT2=2
  • PHYEMAC0RXCOMMADET=2
  • PHYEMAC0RXD0=2
  • PHYEMAC0RXD1=2
  • PHYEMAC0RXD2=2
  • PHYEMAC0RXD3=2
  • PHYEMAC0RXD4=2
  • PHYEMAC0RXD5=2
  • PHYEMAC0RXD6=2
  • PHYEMAC0RXD7=2
  • PHYEMAC0RXDISPERR=2
  • PHYEMAC0RXDV=2
  • PHYEMAC0RXER=2
  • PHYEMAC0RXLOSSOFSYNC0=2
  • PHYEMAC0RXLOSSOFSYNC1=2
  • PHYEMAC0RXNOTINTABLE=2
  • PHYEMAC0RXRUNDISP=2
  • PHYEMAC0SIGNALDET=2
  • PHYEMAC0TXBUFERR=2
  • PHYEMAC0TXGMIIMIICLKIN=2
  • PHYEMAC1COL=2
  • PHYEMAC1CRS=2
  • PHYEMAC1GTXCLK=2
  • PHYEMAC1MCLKIN=2
  • PHYEMAC1MDIN=2
  • PHYEMAC1MIITXCLK=2
  • PHYEMAC1PHYAD0=2
  • PHYEMAC1PHYAD1=2
  • PHYEMAC1PHYAD2=2
  • PHYEMAC1PHYAD3=2
  • PHYEMAC1PHYAD4=2
  • PHYEMAC1RXBUFERR=2
  • PHYEMAC1RXBUFSTATUS0=2
  • PHYEMAC1RXBUFSTATUS1=2
  • PHYEMAC1RXCHARISCOMMA=2
  • PHYEMAC1RXCHARISK=2
  • PHYEMAC1RXCHECKINGCRC=2
  • PHYEMAC1RXCLK=2
  • PHYEMAC1RXCLKCORCNT0=2
  • PHYEMAC1RXCLKCORCNT1=2
  • PHYEMAC1RXCLKCORCNT2=2
  • PHYEMAC1RXCOMMADET=2
  • PHYEMAC1RXD0=2
  • PHYEMAC1RXD1=2
  • PHYEMAC1RXD2=2
  • PHYEMAC1RXD3=2
  • PHYEMAC1RXD4=2
  • PHYEMAC1RXD5=2
  • PHYEMAC1RXD6=2
  • PHYEMAC1RXD7=2
  • PHYEMAC1RXDISPERR=2
  • PHYEMAC1RXDV=2
  • PHYEMAC1RXER=2
  • PHYEMAC1RXLOSSOFSYNC0=2
  • PHYEMAC1RXLOSSOFSYNC1=2
  • PHYEMAC1RXNOTINTABLE=2
  • PHYEMAC1RXRUNDISP=2
  • PHYEMAC1SIGNALDET=2
  • PHYEMAC1TXBUFERR=2
  • PHYEMAC1TXGMIIMIICLKIN=2
  • RESET=2
 
Tool Usage
Command Line History
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx110t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx110t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx110t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx110t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx110t-ff1136-1 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -sd <dname> -nt timestamp -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -detail -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 12 11 0 0 0 0 0
bitgen 22 22 0 0 0 0 0
map 23 23 0 0 0 0 0
ngcbuild 17 17 0 0 0 0 0
ngdbuild 30 23 0 0 0 0 0
par 23 23 0 0 0 0 0
trce 23 23 0 0 0 0 0
xst 71 69 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=true PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_SelectedInstanceHierarchicalPath=/TB_Pico_HOST_Interface PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserBrowsedStrategyFiles=C:/Xilinx/14.2/ISE_DS/ISE/virtex5/data/virtex5_runtime_multithreading.xds
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2012-08-24T14:58:04
PROP_intWbtProjectID=4FFDA24DA2BB4E7EA6749A35F58B5474 PROP_intWbtProjectIteration=40
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_selectedSimRootSourceNode_behav=work.TB_Pico_HOST_Interface PROP_xilxMapReportDetail=true
PROP_xilxSynthKeepHierarchy=Yes PROP_AutoTop=true
PROP_DevFamily=Virtex5 PROP_DevDevice=xc5vlx50t
PROP_DevFamilyPMName=virtex5 PROP_DevPackage=ff1136
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-1
PROP_PreferredLanguage=VHDL FILE_COREGEN=2
FILE_ISIM_EXE=1 FILE_UCF=1
FILE_USERDOC=2 FILE_VHDL=24
 
Core Statistics
Core Type=blk_mem_gen_v7_3
c_addra_width=16 c_addrb_width=16 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=9 c_common_clk=0
c_default_data=0 c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=masked_value
c_enable_32bit_address=0 c_family=virtex5 c_has_axi_id=0 c_has_ena=1
c_has_enb=1 c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0
c_has_mux_output_regs_a=0 c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0
c_has_rsta=1 c_has_rstb=1 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0
c_init_file=BlankString c_init_file_name=no_coe_file_loaded c_inita_val=0 c_initb_val=0
c_interface_type=0 c_load_init_file=0 c_mem_type=2 c_mux_pipeline_stages=0
c_prim_type=1 c_read_depth_a=65536 c_read_depth_b=65536 c_read_width_a=9
c_read_width_b=9 c_rst_priority_a=CE c_rst_priority_b=CE c_rst_type=SYNC
c_rstram_a=0 c_rstram_b=0 c_sim_collision_check=ALL c_use_bram_block=0
c_use_byte_wea=0 c_use_byte_web=0 c_use_default_data=0 c_use_ecc=0
c_use_softecc=0 c_wea_width=1 c_web_width=1 c_write_depth_a=65536
c_write_depth_b=65536 c_write_mode_a=READ_FIRST c_write_mode_b=READ_FIRST c_write_width_a=9
c_write_width_b=9 c_xdevicefamily=virtex5
Core Type=v5_emac_v1_8
c_add_filter_emac0=false c_add_filter_emac1=false c_client_16_emac0=false c_client_16_emac1=false
c_emac0=true c_emac1=false c_has_clock_enable_emac0=false c_has_clock_enable_emac1=false
c_has_dcr=false c_has_gmii_emac0=false c_has_gmii_emac1=true c_has_gpcs_emac0=false
c_has_gpcs_emac1=false c_has_host=true c_has_mdio_emac0=true c_has_mdio_emac1=false
c_has_mii_emac0=false c_has_mii_emac1=false c_has_rgmii_v1_3_emac0=false c_has_rgmii_v1_3_emac1=false
c_has_rgmii_v2_0_emac0=false c_has_rgmii_v2_0_emac1=false c_has_sgmii_emac0=true c_has_sgmii_emac1=false
c_speed_1000_emac0=false c_speed_1000_emac1=true c_speed_100_emac0=false c_speed_100_emac1=false
c_speed_10_emac0=false c_speed_10_emac1=false c_tri_speed_emac0=true c_tri_speed_emac1=false
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=4 NGDBUILD_NUM_FD=225 NGDBUILD_NUM_FDE=645 NGDBUILD_NUM_FDPE=8
NGDBUILD_NUM_FDR=207 NGDBUILD_NUM_FDRE=184 NGDBUILD_NUM_FDRS=4 NGDBUILD_NUM_FDRSE=10
NGDBUILD_NUM_FDS=15 NGDBUILD_NUM_FDSE=8 NGDBUILD_NUM_GND=28 NGDBUILD_NUM_GTP_DUAL=2
NGDBUILD_NUM_IBUF=11 NGDBUILD_NUM_IBUFGDS=2 NGDBUILD_NUM_INV=60 NGDBUILD_NUM_IOBUF=1
NGDBUILD_NUM_LUT1=127 NGDBUILD_NUM_LUT2=162 NGDBUILD_NUM_LUT3=234 NGDBUILD_NUM_LUT4=179
NGDBUILD_NUM_LUT5=205 NGDBUILD_NUM_LUT6=490 NGDBUILD_NUM_MUXCY=373 NGDBUILD_NUM_MUXF7=89
NGDBUILD_NUM_MUXF8=36 NGDBUILD_NUM_OBUF=53 NGDBUILD_NUM_OBUFT=1 NGDBUILD_NUM_RAM16X1D=8
NGDBUILD_NUM_RAM32X1S=10 NGDBUILD_NUM_RAM64X1S=8 NGDBUILD_NUM_RAMB16=7 NGDBUILD_NUM_RAMB36_EXP=32
NGDBUILD_NUM_SRLC16E=26 NGDBUILD_NUM_TEMAC=2 NGDBUILD_NUM_VCC=19 NGDBUILD_NUM_XORCY=388
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=4 NGDBUILD_NUM_FD=225 NGDBUILD_NUM_FDE=645 NGDBUILD_NUM_FDPE=8
NGDBUILD_NUM_FDR=207 NGDBUILD_NUM_FDRE=184 NGDBUILD_NUM_FDRS=4 NGDBUILD_NUM_FDRSE=10
NGDBUILD_NUM_FDS=15 NGDBUILD_NUM_FDSE=8 NGDBUILD_NUM_GND=28 NGDBUILD_NUM_GTP_DUAL=2
NGDBUILD_NUM_IBUF=24 NGDBUILD_NUM_IBUFGDS=2 NGDBUILD_NUM_INV=60 NGDBUILD_NUM_LUT1=127
NGDBUILD_NUM_LUT2=162 NGDBUILD_NUM_LUT3=234 NGDBUILD_NUM_LUT4=179 NGDBUILD_NUM_LUT5=205
NGDBUILD_NUM_LUT6=490 NGDBUILD_NUM_MUXCY=373 NGDBUILD_NUM_MUXF7=89 NGDBUILD_NUM_MUXF8=36
NGDBUILD_NUM_OBUF=53 NGDBUILD_NUM_OBUFT=2 NGDBUILD_NUM_RAM32X1S=10 NGDBUILD_NUM_RAM64X1S=8
NGDBUILD_NUM_RAMB16=7 NGDBUILD_NUM_RAMB36_EXP=32 NGDBUILD_NUM_SRLC16E=26 NGDBUILD_NUM_TEMAC=2
NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=19 NGDBUILD_NUM_XORCY=388
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc5vlx50t-1-ff1136 -top=<design_top> -opt_mode=Speed -opt_level=1
-power=NO -iuc=NO -keep_hierarchy=Yes -netlist_hierarchy=As_Optimized
-rtlview=Yes -glob_opt=AllClockNets -read_cores=YES -sd=<No customer specific name>
-write_timing_constraints=NO -cross_clock_analysis=NO -bus_delimiter=<> -slice_utilization_ratio=100
-bram_utilization_ratio=100 -dsp_utilization_ratio=100 -reduce_control_sets=Off -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-use_dsp48=Auto -iobuf=YES -max_fanout=100000 -bufg=32
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Auto
-use_sync_set=Auto -use_sync_reset=Auto -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5