Splitter_TOP Project Status (05/21/2015 - 10:24:59)
Project File: ML505_Splitter_03.xise Parser Errors: No Errors
Module Name: Splitter_TOP Implementation State: Programming File Generated
Target Device: xc5vlx50t-1ff1136
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
424 Warnings (85 new, 169 filtered)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 1,298 28,800 4%  
    Number used as Flip Flops 1,298      
Number of Slice LUTs 1,424 28,800 4%  
    Number used as logic 1,358 28,800 4%  
        Number using O6 output only 1,131      
        Number using O5 output only 118      
        Number using O5 and O6 109      
    Number used as Memory 52 7,680 1%  
        Number used as Dual Port RAM 8      
            Number using O5 and O6 8      
        Number used as Single Port RAM 18      
            Number using O6 output only 18      
        Number used as Shift Register 26      
            Number using O6 output only 26      
    Number used as exclusive route-thru 14      
Number of route-thrus 136      
    Number using O6 output only 130      
    Number using O5 output only 4      
    Number using O5 and O6 2      
Number of occupied Slices 842 7,200 11%  
Number of LUT Flip Flop pairs used 1,946      
    Number with an unused Flip Flop 648 1,946 33%  
    Number with an unused LUT 522 1,946 26%  
    Number of fully used LUT-FF pairs 776 1,946 39%  
    Number of unique control sets 164      
    Number of slice register sites lost
        to control set restrictions
338 28,800 1%  
Number of bonded IOBs 61 480 12%  
    Number of LOCed IOBs 61 61 100%  
    Number of bonded IPADs 12      
        Number of LOCed IPADs 12 12 100%  
    Number of bonded OPADs 8      
        Number of LOCed OPADs 8 8 100%  
Number of BlockRAM/FIFO 36 60 60%  
    Number using BlockRAM only 36      
        Number of 36k BlockRAM used 32      
        Number of 18k BlockRAM used 7      
    Total Memory used (KB) 1,278 2,160 59%  
Number of BUFG/BUFGCTRLs 4 32 12%  
    Number used as BUFGs 4      
Number of BUFDSs 2 6 33%  
Number of GTP_DUALs 2 6 33%  
Number of TEMACs 2 2 100%  
Average Fanout of Non-Clock Nets 3.94      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentšt 21. 5 10:22:50 20150321 Warnings (20 new, 155 filtered)13 Infos (0 new, 0 filtered)
Translation ReportCurrentšt 21. 5 10:22:58 2015021 Warnings (0 new, 0 filtered)0
Map ReportCurrentšt 21. 5 10:23:50 2015067 Warnings (65 new, 2 filtered)155 Infos (18 new, 0 filtered)
Place and Route ReportCurrentšt 21. 5 10:24:14 2015014 Warnings (0 new, 12 filtered)1 Info (0 new, 0 filtered)
Power Report     
Post-PAR Static Timing ReportCurrentšt 21. 5 10:24:23 2015004 Infos (0 new, 0 filtered)
Bitgen ReportCurrentšt 21. 5 10:24:51 201501 Warning (0 new, 0 filtered)1 Info (0 new, 0 filtered)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentšt 21. 5 10:24:52 2015
WebTalk Log FileCurrentšt 21. 5 10:24:58 2015

Date Generated: 05/21/2015 - 10:24:59