Project Statistics |
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PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_SelectedInstanceHierarchicalPath=/TB_Pico_HOST_Interface |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserBrowsedStrategyFiles=C:/Xilinx/14.2/ISE_DS/ISE/virtex5/data/virtex5_runtime_multithreading.xds |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2012-08-24T14:58:04 |
PROP_intWbtProjectID=4FFDA24DA2BB4E7EA6749A35F58B5474 |
PROP_intWbtProjectIteration=40 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_selectedSimRootSourceNode_behav=work.TB_Pico_HOST_Interface |
PROP_xilxMapReportDetail=true |
PROP_xilxSynthKeepHierarchy=Yes |
PROP_AutoTop=true |
PROP_DevFamily=Virtex5 |
PROP_DevDevice=xc5vlx50t |
PROP_DevFamilyPMName=virtex5 |
PROP_DevPackage=ff1136 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-1 |
PROP_PreferredLanguage=VHDL |
FILE_COREGEN=2 |
FILE_ISIM_EXE=1 |
FILE_UCF=1 |
FILE_USERDOC=2 |
FILE_VHDL=24 |