/**
 * \file
 *
 * \brief FPU support for SAM.
 *
 * Copyright (c) 2013 Atmel Corporation. All rights reserved.
 *
 * \asf_license_start
 *
 * \page License
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 *
 * 3. The name of Atmel may not be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * 4. This software may only be redistributed and used in connection with an
 *    Atmel microcontroller product.
 *
 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 * \asf_license_stop
 *
 */

#ifndef _FPU_H_INCLUDED_
#define _FPU_H_INCLUDED_

/** Address for ARM CPACR */
#define ADDR_CPACR 0xE000ED88

/** CPACR Register */
#define REG_CPACR  (*((volatile uint32_t *)ADDR_CPACR))

/**
 * Enable FPU
 */
inline static void fpu_enable(void)
{
	__asm volatile ("// CPACR is located at address 0xE000ED88 \n\t"
			"LDR.W R0, =0xE000ED88 \n\t"
			"// Read CPACR \n\t"
			"LDR R1, [R0] \n\t"
			"// Set bits 20-23 to enable CP10 and CP11 coprocessors \n\t"
			"ORR R1, R1, #(0xF << 20) \n\t"
			"// Write back the modified value to the CPACR \n\t"
			"STR R1, [R0] \n\t"
			"// wait for store to complete \n\t"
			"DSB \n\t"
			"// reset pipeline now the FPU is enabled \n\t"
			"ISB \n\t");

	__asm volatile ("//nastaveni ukladani floating statusu na stack \n\t"
			"MRS R0, CONTROL \n\t"
			"ORR R0, R0, #(0x4) \n\t"
			"MSR CONTROL, R0");

}

/**
 * Disable FPU
 */
inline static void fpu_disable(void)
{
	__asm volatile ("// CPACR is located at address 0xE000ED88 \n\t"
				"LDR.W R0, =0xE000ED88 \n\t"
				"// Read CPACR \n\t"
				"LDR R1, [R0] \n\t"
				"// Cleas bits 20-23 to disable CP10 and CP11 coprocessors \n\t"
				"BIC.W R1, R1, #(0xF << 20) \n\t"
				"// Write back the modified value to the CPACR \n\t"
				"STR R1, [R0] \n\t"
				"// wait for store to complete \n\t"
				"DSB \n\t"
				"// reset pipeline now the FPU is enabled \n\t"
				"ISB \n\t");

	__asm volatile ("//zruseni ukladani floating statusu na stack \n\t"
			"MRS R0, CONTROL \n\t"
			"BIC.W R0, R0, #0x4 \n\t"
			"MSR CONTROL, R0");


}

/**
 * Check if FPU is enabled
 */
inline static bool_t fpu_is_enabled(void)
{
	return (REG_CPACR & (0xFu << 20));
}

#endif /* _FPU_H_INCLUDED_ */
