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  • A Chaotic IP Watermarking in Physical Layout Level Based on FPGA 

    W. Liang, X. Sun, Z. Xia, D. Sun, J. Long (Společnost pro radioelektronické inženýrství, 2011-04)
    A new chaotic map based IP (Intellectual Property) watermarking scheme at physical design level is presented. An encrypted watermark is embedded into the physical layout of a circuit by configuring LUT (Lookup Table) as ...