Now showing items 1-2 of 2

  • Area-Efficient Hardware Architectures of MISTY1 Block Cipher 

    Yasir, A.; Wu, N.; Chen, X.; Rehan Yahya, M. (Společnost pro radioelektronické inženýrství, 2018-06)
    In this paper, state-of-the-art hardware implementations of MISTY1 block cipher are presented for area-constrained wireless applications. The proposed MISTY1 architectures are characterized of highly optimized transformation ...
  • High-Efficient Parallel CAVLC Encoders on Heterogeneous Multicore Architectures 

    Su, H. Y.; Wen, M.; Ren, J.; Wu, N.; Chai, J.; Zhang, C. Y. (Společnost pro radioelektronické inženýrství, 2012-04)
    This article presents two high-efficient parallel realizations of the context-based adaptive variable length coding (CAVLC) based on heterogeneous multicore processors. By optimizing the architecture of the CAVLC encoder, ...