Now showing items 1-3 of 3

  • Acceleration Unit for HTTP Headers Identification in FPGA 

    Bryndza, Ivan (Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií, 2015)
    This paper presents a hardware accelerated identification of HTTP protocol headers, since HTTP is the most used protocol on the Internet. We have designed a hardware architecture, which will be used for detection of HTTP ...
  • Akcelerace identifikace HTTP hlaviček v obvodech FPGA 

    Bryndza, Ivan
    Táto bakalárska práca sa zaoberá hardvérovou akceleráciou identifikácie hlavičiek HTTP protokolu, ktorý je na internete veľmi rozšírený. Cieľom je navrhnúť a implementovať hardvérovú architektúru, ktorá bude slúžiť na ...
  • FPGA-based Low Latency Inverse QRD Architecture for Adaptive Beamforming in Phased Array Radars 

    Irfan, R.; Rasheed, H.; Toor, W. A. (Společnost pro radioelektronické inženýrství, 2017-09)
    The main objective of this paper is to facilitate the adaptive beamforming which is one of the most challenging task in phased array radars receivers. Recursive least square (RLS) is considered as the most well suited ...