Fakulta elektrotechniky a komunikačních technologiíhttp://hdl.handle.net/11012/309942019-08-22T20:37:53Z2019-08-22T20:37:53ZPreparation and Characterization of Carbon Paste Electrode Bulk-Modified with Multiwalled Carbon Nanotubes and Its Application in a Sensitive Assay of Antihyperlipidemic Simvastatin in Biological SamplesAmirmansoor, AshrafiRichtera, Lukášhttp://hdl.handle.net/11012/1805192019-08-20T01:03:36Z2019-06-02T00:00:00ZPreparation and Characterization of Carbon Paste Electrode Bulk-Modified with Multiwalled Carbon Nanotubes and Its Application in a Sensitive Assay of Antihyperlipidemic Simvastatin in Biological Samples
Amirmansoor, Ashrafi; Richtera, Lukáš
Determination of an antihyperlipidemic drug simvastatin (SIM) was carried out using a carbon paste electrode bulk-modified with multiwalled carbon nanotubes (MWCNT-CPE). Scanning electrochemical microscopy (SECM), scanning electron microscopy (SEM), and atomic force microscopy (AFM) were used for the characterization of the prepared electrodes. Different electrodes were prepared varying in mass percentage of MWCNTs to find out the optimum amount of MWCNTs in the paste. The MWCNT-CPE in which the mass percentage of MWCNTs was 25% (w/w) was found as the optimum. Then, the prepared electrode was used in a mechanistic study and sensitive assay of SIM in pharmaceutical dosage form and a spiked human plasma sample using differential pulse voltammetry (DPV). The prepared electrode shows better sensitivity compared to the bare carbon paste and glassy carbon electrode (GCE). The detection limit and the limit of quantification were calculated to be 2.4 x 10(-7) and 8 x 10(-7), respectively. The reproducibility of the electrode was confirmed by the low value of the relative standard deviation (RSD% = 4.8%) when eight measurements of the same sample were carried out. Determination of SIM in pharmaceutical dosage form was successfully performed with a bias of 0.3% and relative recovery rate of 99.7%. Furthermore, the human plasma as a more complicated matrix was spiked with a known concentration of SIM and the spiking recovery rate was determined with the developed method to be 99.5%.
2019-06-02T00:00:00ZComparative Study of Op-Amp-based Integrators Suitable for Fractional-Order Controller DesignHerencsár, NorbertKartci, AslihanYildiz, Hacer A.Šotner, RomanDvořák, JanKubánek, DavidJeřábek, JanKoton, Jaroslavhttp://hdl.handle.net/11012/1805132019-07-31T01:04:58Z2019-07-01T00:00:00ZComparative Study of Op-Amp-based Integrators Suitable for Fractional-Order Controller Design
Herencsár, Norbert; Kartci, Aslihan; Yildiz, Hacer A.; Šotner, Roman; Dvořák, Jan; Kubánek, David; Jeřábek, Jan; Koton, Jaroslav
In this paper, a fractional-order capacitor (FOC) of an order = 0.89 (i.e. constant phase angle –80.1 degree) was emulated via Valsa RC network with five branches. The network component values were optimized using modified least squares quadratic method in a wide frequency range of 100 mHz–1 kHz (i.e. 4 decades) and maximum relative phase error 0.78% was obtained. The design specification corresponds to a speed control system of an armature controlled DC motor, which is often used in control theory. Overall performance evaluation shows the product of evaluated key features (e.g. phase angle deviation and absolute values of relative phase, impedance, and pseudocapacitance errors) for the optimized FOC is 13.3% less than the one obtained via Valsa approximation. The behavior of Op-Amp-based non-inverting configurations of analogue fractional-order integral operator s– employing the optimized FOC, where 0 < < 1, is compared. The behavior of studied integrator circuits is confirmed by SPICE simulations using the readily available Texas Instruments TL072 low-noise Op-Amp macromodel, which is commonly used in electronics.
2019-07-01T00:00:00ZDesign of Fractional-Order Integrator Controlled by Single Voltage GainŠotner, RomanPetržela, JiříJeřábek, JanHerencsár, NorbertAndriukaitis, Dariushttp://hdl.handle.net/11012/1805122019-07-31T01:04:51Z2019-07-01T00:00:00ZDesign of Fractional-Order Integrator Controlled by Single Voltage Gain
Šotner, Roman; Petržela, Jiří; Jeřábek, Jan; Herencsár, Norbert; Andriukaitis, Darius
This work presents analyses of interaction of fractional- and integer-order transfer functions when their responses are added together by simple linear operation of sum. The mathematical background is very complex but practical consequences may be very useful for further design of electronically reconfigurable circuits including modification of shape of the resulting magnitude and phase responses. Described approach allows control of constant phase shift in limited operational bandwidth by single parameter that is documented by PSpice simulations with models of common of-the-shelf active elements.
2019-07-01T00:00:00ZVDIBA-Based Fractional-Order Oscillator DesignKartci, AslihanHerencsár, NorbertDvořák, JanVrba, Kamilhttp://hdl.handle.net/11012/1805102019-07-30T06:55:34Z2019-07-01T00:00:00ZVDIBA-Based Fractional-Order Oscillator Design
Kartci, Aslihan; Herencsár, Norbert; Dvořák, Jan; Vrba, Kamil
This paper deals with a voltage-mode integer- and fractional-order oscillator design providing compact and simple CMOS structure. The proposed circuit consists of only one grounded/floating capacitor, one grounded/floating resistor, and one high-performance and versatile active element so-called voltage differencing inverting buffered amplifier (VDIBA), employing only six transistors. Compared with the corresponding already introduced fractional-order oscillators, it offers the benefit of low transistor count. In addition, it offers the well-known advantages of fractional-order oscillators about the capability for achieving very low and high oscillation frequencies with reasonable component values. The design parameters of the proposed oscillator can be electronically adjusted via change of order of the fractional-order capacitor and/or by means of bias current of the internal transconductance of the VDIBA. Theoretical results are verified by SPICE simulations using TSMC 0.18 m level-7 LO EPI SCN018 CMOS process parameters with ±0.9 V supply voltages.
2019-07-01T00:00:00Z