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dc.contributor.authorWalletzký, Ondřej
dc.date.accessioned2020-05-07T09:40:28Z
dc.date.available2020-05-07T09:40:28Z
dc.date.issued2017cs
dc.identifier.citationProceedings of the 23st Conference STUDENT EEICT 2017. s. 251-253. ISBN 978-80-214-5496-5cs
dc.identifier.isbn978-80-214-5496-5
dc.identifier.urihttp://hdl.handle.net/11012/187098
dc.description.abstractThis article describes design and implementation of Remote Memory Access Protocol controller, namely the initiator module specified in the ECSS-E-ST-50-52C standard. It provides general description of its architecture and describes some of its subcomponents. Finally, it summarizes resource utilization and maximum theoretical clock frequency for different configurations when synthesized for Spartan-3 FPGA chip.en
dc.formattextcs
dc.format.extent251-253cs
dc.format.mimetypeapplication/pdfen
dc.language.isocscs
dc.publisherVysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologiícs
dc.relation.ispartofProceedings of the 23st Conference STUDENT EEICT 2017en
dc.relation.urihttp://www.feec.vutbr.cz/EEICT/cs
dc.rights© Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologiícs
dc.subjectRMAPen
dc.subjectSpaceWireen
dc.subjectVHDLen
dc.subjectFPGAen
dc.subjectAMBAen
dc.subjectAHBen
dc.titleRemote Memory Access Protocol Controller For Spacewire Networken
eprints.affiliatedInstitution.departmentFakulta elektrotechniky a komunikačních technologiícs
but.event.date27.04.2017cs
but.event.titleStudent EEICT 2017cs
dc.rights.accessopenAccessen
dc.type.driverconferenceObjecten
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen


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