Now showing items 11-15 of 15
FPGA Based Test Module for Error Bit Evaluation in Serial Links
(Společnost pro radioelektronické inženýrství, 2006-04)
A test module for serial links is described. In the link transmitter, one module generates pseudorandom pulse signal that is transmitted by the link. Second module located in the link receiver generates the same signal and ...
In-system Jitter Measurement Based on Blind Oversampling Data Recovery
(Společnost pro radioelektronické inženýrství, 2012-04)
The paper describes a novel method for simple estimation of jitter contained in a received digital signal. The main objective of our research was to enable a non-invasive measurement of data link properties during a regular ...
An FPGA Based Implementation of a CFAR Processor Applied to a Pulse-Compression Radar System
(Společnost pro radioelektronické inženýrství, 2014-04)
A hardware architecture that implements a CFAR processor including six variants of the CFAR algorithm based on linear and nonlinear operations for radar applications is presented. Since some implemented CFAR algorithms ...
Pipelined Two-Operand Modular Adders
(Společnost pro radioelektronické inženýrství, 2015-04)
Pipelined two-operand modular adder (TOMA) is one of basic components used in digital signal processing (DSP) systems that use the residue number system (RNS). Such modular adders are used in binary/residue and residue/binary ...
Design and Implementation of a FPGA and DSP Based MIMO Radar Imaging System
(Společnost pro radioelektronické inženýrství, 2015-06)
The work presented in this paper is aimed at the implementation of a real-time multiple-input multiple-output (MIMO) imaging radar used for area surveillance. In this radar, the equivalent virtual array method and time-division ...