Design of Novel CMOS DCCII with Reduced Parasitics and its All-Pass Filter Applications
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In this paper, a novel translinear loop based, high performance Complementary Metal-Oxide-Semiconductor (CMOS) second-generation differential current conveyor (DCCII) is introduced. By using super source follower transistors, very low equivalent impedances are obtained at input terminals xn and xp. In addition, new voltage-mode (VM) and current-mode (CM) first-order all-pass filters (APFs) are proposed to highlight the performance of the designed CMOS DCCII. The designed CMOS implementation is simulated with HSpice using AMS 0.35 µm real process parameters. It consumes only 1.3 mW power with using +/- 1.25 V power supply voltages. The simulation results of the proposed CMOS DCII circuit and the experimental results for designed VM APF are in very good agreement with the theoretical ones.
KeywordsAnalog signal processing, all-pass filter, current-mode, voltage-mode, DCCII, reduced parasitic, super source follower, translinear loop
Document typePeer reviewed
Document versionFinal PDF
SourceElektronika Ir Elektrotechnika. 2016, vol. 22, issue 6, p. 46-50.
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