An FPGA Based Implementation of a CFAR Processor Applied to a Pulse-Compression Radar System
A hardware architecture that implements a CFAR processor including six variants of the CFAR algorithm based on linear and nonlinear operations for radar applications is presented. Since some implemented CFAR algorithms require sorting the input samples, the two sorting solutions are investigated. The first one is iterative, and it is suitable when incoming data clock is several times less than sorting clock. The second sorter is very fast by exploiting a high degree of parallelism. The architecture is on-line reconfigurable both in terms of CFAR method and in terms of the number of reference and guard cells. The architecture was developed for coherent radar with pulse compression. Besides dealing with surface clutter and multiple target situations, such radar detector is often faced with high side-lobes at the compression filter output when strong target presents in his sight. The results of implementing the architecture on a Field Programmable Gate Array (FPGA) are presented and discussed.
Document typePeer reviewed
Document versionFinal PDF
SourceRadioengineering. 2014, vol. 23, č. 1, s. 73-83. ISSN 1210-2512
- 2014/1