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Improvement of Bit Error Rate in Free Space Optical Link
(Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií, 2016)
The article describes an inovative bit error rate reduction technique principle and its practical implementation. The design is implemented in an FPGA and can be combined with other more conventional BER reduction techniques. ...
Clock Domain Crossing Interfaces
(Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií, 2015)
This work presents an easy-to-use library of clock domain crossing modules and a methodology for it's use. These crossings are inevitable in moderately complex firmware designs. Incorrectly implemented clock domain crossing ...
Implementation of AES Algorithm on FPGA
(Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií, 2015)
This paper presents a VHDL (Very High Speed Integrated Circuit Hardware Description Language) implementation of 128-bit AES (Advanced Encryption Standard) on FPGA card (FieldProgrammable Gate Array) using Virtex-7 FPGA ...
BLDC Motor Hil Real-Time Simulation On ZYNQ
(Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií, 2017)
This paper is focused on real-time simulation of BLDC motor on SOC ZYNQ device. The simplified model of BLDC motor in Matlab/Simulink is introduced. Next, the scale method based on physical principles of motor is described. ...
Cipher Twofish Implementation On Fpga Board
(Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií, 2018)
This paper deals with nowadays hot topic, which is data security and secure communication. It describes solution which uses Twofish cipher to ensure confidentiality of data. The cipher Is implemented in VHDL language and ...
High-Speed Anomaly Detection System Using Entropy Calculation On Fpga
(Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií, 2017)
This article discusses the use of entropy calculation on Field Programmable Gate Array (FPGA) for identifying anomalies in data communication. The article is focused on three type of entropy and described hardware-accelerated ...
Remote Memory Access Protocol Controller For Spacewire Network
(Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií, 2017)
This article describes design and implementation of Remote Memory Access Protocol controller, namely the initiator module specified in the ECSS-E-ST-50-52C standard. It provides general description of its architecture and ...
Control Unit For CubeSat
(Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií, 2017)
The aim of the project was to design a CubeSat control unit. The board is composed of commercial parts yet reliable in the space environment. Because of its benefits, an FPGA was selected as the core of the board. The FPGA ...
Application Of Fpga In Multilevel Inverters
(Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií, 2017)
In this paper, a single-phase five-level Active Neutral-Point Clamped inverter design is presented. The paper is focusing chiefly on control hardware and control strategy for 5-level PWM with active balancing of the charge ...
High Precision Reference Position Generator for Motor Control in FPGA
(Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií, 2016)
The paper deals with an architecture of a high precision reference position generator for a motor controller implemented in FPGA. The architecture was developed to achieve high accuracy and tunability with concern to ...