Low-Voltage MOS Current Mode Logic Multiplexer
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In this paper, a new low-voltage MOS current mode logic (MCML) multiplexer based on the triple-tail cell concept is proposed. An analytical model for static parameters is formulated and is applied to develop a design approach for the proposed low-voltage MCML multiplexer. The delay of the proposed low-voltage MCML multiplexer is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage MCML multiplexer is analyzed for the three design cases namely high-speed, power-efficient, and low-power. Finally, a comparison in performance of the proposed low-voltage MCML multiplexer with the traditional MCML multiplexer is carried out for all the cases.
Typ dokumentuRecenzovaný dokument
Verze dokumentuFinální verze PDF
Zdrojový dokumentRadioengineering. 2013, vol. 22, č. 1, s. 259-268. ISSN 1210-2512
- 2013/1