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dc.contributor.authorCabal, J.
dc.date.accessioned2015-08-25T08:42:46Z
dc.date.available2015-08-25T08:42:46Z
dc.date.issued2015cs
dc.identifier.citationProceedings of the 21st Conference STUDENT EEICT 2015. s. 37-39. ISBN 978-80-214-5148-3cs
dc.identifier.isbn978-80-214-5148-3
dc.identifier.urihttp://hdl.handle.net/11012/42923
dc.description.abstractThis work presents an easy-to-use library of clock domain crossing modules and a methodology for it's use. These crossings are inevitable in moderately complex firmware designs. Incorrectly implemented clock domain crossing modules can lead to data corruption or data loss. For correct functionality of these crossings it is necessary to apply correct constraints. Automatic application of contraints is a part of the created library. Its easy use is also supported by the methodology for selection of correct clock domain crossing module in the form of a decision tree.en
dc.formattextcs
dc.format.extent37-39cs
dc.format.mimetypeapplication/pdfen
dc.language.isocscs
dc.publisherVysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologiícs
dc.relation.ispartofProceedings of the 21st Conference STUDENT EEICT 2015en
dc.relation.urihttp://www.feec.vutbr.cz/EEICT/cs
dc.rights© Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologiícs
dc.subjectFPGAen
dc.subjectCDCen
dc.subjectmetastabilityen
dc.subjectVivadoen
dc.titleClock Domain Crossing Interfacesen
eprints.affiliatedInstitution.departmentFakulta elektrotechniky a komunikačních technologiícs
but.event.date23.04.2015cs
but.event.titleStudent EEICT 2015cs
dc.rights.accessopenAccessen
dc.type.driverconferenceObjecten
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen


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