FPGA Implementation of a Frame Synchronization Algorithm for Powerline Communications
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This paper presents an FPGA implementation of a pilot–based time synchronization scheme employing orthogonal frequency division multiplexing for powerline communication channels. The functionality of the algorithm is analyzed and tested over a real powerline residential network. For this purpose, an appropriate transmitter circuit, implemented by an FPGA, and suitable coupling circuits are constructed. The system has been developed using VHDL language on Nallatech XtremeDSP development kits. The communication system operates in the baseband up to 30 MHz. Measurements of the algorithm's good performance in terms of the number of detected frames and timing offset error are taken and compared to simulations of existing algorithms.
KeywordsField Programmable Gate Arrays (FPGAs), frequency division multiplexing, power line communications, frame synchronization
Document typePeer reviewed
Document versionFinal PDF
SourceRadioengineering. 2009, vol. 18, č. 3, s. 325-329. ISSN 1210-2512
- 2009/3