A Verilog-A Based Fractional Frequency Synthesizer Model for Fast and Accurate Noise Assessment
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This paper presents a new strategy to simulate fractional frequency synthesizer behavioral models with better performance and reduced simulation time. The models are described in Verilog-A with accurate phase noise predictions and they are based on a time jitter to power spectral density transformation of the principal noise sources in a synthesizer. The results of a fractional frequency synthesizer simulation is compared with state of the art Verilog-A descriptions showing a reduction of nearly 20 times. In addition, experimental results of a fractional frequency synthesizer are compared to the simulation results to validate the proposed model.
Document typePeer reviewed
Document versionFinal PDF
SourceRadioengineering. 2016 vol. 25, č. 1, s. 89-97. ISSN 1210-2512
- 2016/1