Synchronous Counters Implemented in the PLD Devices
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The implementability of synchronous counters in the Programmable Logic Devices (PLD) is discussed in this paper. The most commonly used counters are analysed from this point of view. The expressions for their individual bits are given and the number of product terms is derived to allow to estimate the size of the particular counter which can be implemented in the chosen PLD.
Document typePeer reviewed
Document versionFinal PDF
SourceRadioengineering. 1999, vol. 8, č. 1, s. 14-18. ISSN 1210-2512
- 1999/1