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dc.contributor.authorHarakal, M.
dc.contributor.authorChmurny, J.
dc.date.accessioned2016-05-05T12:02:11Z
dc.date.available2016-05-05T12:02:11Z
dc.date.issued1997-12cs
dc.identifier.citationRadioengineering. 1997, vol. 6, č. 4, s. 1-5. ISSN 1210-2512cs
dc.identifier.issn1210-2512
dc.identifier.urihttp://hdl.handle.net/11012/58371
dc.description.abstractThis paper describes the design and hardware implementation of the Tesseral Processor (TP) with Programmable Logic Devices (PLD). The TP can be used for image processing based on hierarchical data structures as Linear QuadTree (LQT).en
dc.formattextcs
dc.format.extent1-5cs
dc.format.mimetypeapplication/pdfen
dc.language.isoencs
dc.publisherSpolečnost pro radioelektronické inženýrstvícs
dc.relation.ispartofRadioengineeringcs
dc.relation.urihttp://www.radioeng.cz/fulltexts/1997/97_04_01.pdfcs
dc.rightsCreative Commons Attribution 3.0 Unported Licenseen
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/en
dc.subjectquadtree representationen
dc.subjectlinear quadtreeen
dc.subjecttesseral addressingen
dc.subjecttesseral arithmeticen
dc.subjecttesseral arithmetic uniten
dc.subjecttesseral control uniten
dc.subjecttesseral processoren
dc.titleThe Tesseral Processor for Image Processing Based on Hierarchical Data Structuresen
eprints.affiliatedInstitution.facultyFakulta eletrotechniky a komunikačních technologiícs
dc.coverage.issue4cs
dc.coverage.volume6cs
dc.rights.accessopenAccessen
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen


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