A CMOS Morlet Wavelet Generator

The design and characterization of a CMOS circuit for Morlet wavelet generation is introduced. With the proposed Morlet wavelet circuit, it is possible to reach a~low power consumption, improve standard deviation (σ) control and also have a small form factor. A prototype in a double poly, three metal layers, 0.5 µm CMOS process from MOSIS foundry was carried out in order to verify the functionality of the proposal. However, the design methodology can be extended to different CMOS processes. According to the performance exhibited by the circuit, may be useful in many different signal processing tasks such as nonlinear time-variant systems.

Keywords

CMOS, wavelet, Morlet, analog multiplier, weak-inversion

Citation

Radioengineering. 2017 vol. 26, č. 1, s. 263-268. ISSN 1210-2512
http://www.radioeng.cz/fulltexts/2017/17_01_0263_0268.pdf

Document type

Peer-reviewed

Document version

Published version

Language of document

en

Document licence

Creative Commons Attribution 4.0 International
http://creativecommons.org/licenses/by/4.0/