A 159 μW, Fourth Order, Feedforward, Mutli-bit Sigma Delta Modulator for 100 kHz Bandwidth Image Sensors in 65-nm CMOS Process
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A fourth-order, three-stage, feedforward cascade sigma-delta modulator (ƩΔM) for CMOS image sensor applications is realized in low leakage, high threshold voltage 65 nm CMOS standard process. A top down CAD methodology is used for the design of building blocks, which involves statistical and simulation optimization at different stages of modulator. The multi-bit ƩΔ architecture employs OTA sharing technique with the dual integrating scheme at the first stage and the gain boosted pseudo-differential class-C inverters as OTAs for the rest two stages for low area and power consumption. The operation of proposed ƩΔM is validated through post-layout simulations, considering worst case. The ƩΔM operates at a power supply of 1-V offering a peak signal-to-ratio of 92 dB and a peak signal-to-noise plus distortion ratio of 89 dB for a signal bandwidth of 100 kHz. The overall power and estimated area consumed by the ƩΔM including auxiliary blocks is 159 µW and 101.2 mm2, respectively.
KeywordsAnalog front end, CMOS image sensor, sigma-delta modulator, signal-to noise ratio, switch capacitor circuits, gain boosted technology, dynamic element matching
Document typePeer reviewed
Document versionFinal PDF
SourceRadioengineering. 2018 vol. 27, č. 2, s. 519-531. ISSN 1210-2512
- 2018/2