Flood attacks generation
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Proposal of a high speed packet flooding device is presented in this paper. The product is based on the FPGA (Field-programmable Gate Array) platform, developed in VHDL (Very high speed integrated circuit Hardware Description Language) and set into the NetCOPE environment. It uses an existing solution of packet generator. Once done, it should be implemented on a COMBO-80G board to serve as a network stressing tool.
KeywordsFPGA, VHDL, NetCOPE, Denial of Service, DoS, network attack, network tester, packet generator
Document typePeer reviewed
Document versionFinal PDF
SourceProceedings of the 22nd Conference STUDENT EEICT 2016. s. 25-27. ISBN 978-80-214-5350-0
- Student EEICT 2016