Instruction Mapping Process on the VLIW Architectures

Thumbnail
Date
2016
Author
Altmetrics
Metadata
Show full item record
Abstract
This paper deals with the process of instruction mapping on the digital signal processors. This process is used by the newly developed tool, which is designed for generating low-level assembly code for very long instruction word processors. The tool is suitable for creating cores of the signal processing algorithms.
Keywords
instruction mapping, low-level, digital signal processing, very long instruction word
Persistent identifier
http://hdl.handle.net/11012/83961
Document type
Peer reviewed
Document version
xmlui.vut.verze.Publishers's version
Source
Proceedings of the 22nd Conference STUDENT EEICT 2016. s. 385-389. ISBN 978-80-214-5350-0
http://www.feec.vutbr.cz/EEICT/
Collections
Citace PRO