Instruction Mapping Process on the VLIW Architectures
This paper deals with the process of instruction mapping on the digital signal processors. This process is used by the newly developed tool, which is designed for generating low-level assembly code for very long instruction word processors. The tool is suitable for creating cores of the signal processing algorithms.
Document typePeer reviewed
Document versionFinal PDF
SourceProceedings of the 22nd Conference STUDENT EEICT 2016. s. 385-389. ISBN 978-80-214-5350-0
- Student EEICT 2016