ŽÁDNÍK, J. Implementation of Fast Fourier Transformation on Transport Triggered Architecture [online]. Brno: Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií. 2017.

Posudek vypracoval prof. Jarmo Takala, Tampere University of Technology. Jakub has completed his work as I expected. Originally he was planning to implement a complete audio application exploiting FFT with the processor which he designed, but I knew that optimizing the FFT processor is already a large effort. He has studied the previous FFT implementation and figured out the details of mixed-radix FFT and the interleaved instruction schedule on optimized architecture and, in particular, parallel memory organization supporting the required memory bandwidth. He implemented the mixed radix FFT with several approaches for verification purpose and finalized architecture partially exploiting existing functional units. He manually scheduled FFT kernels and based on this experiment he customized an architecture with loop buffer such that the previous kernel (over 10 instructions) was realized with a single instruction. In order to support this he had to also develop rotating registers for intermediate variables from multiple iterations of the kernel. He developed VHDL description and verified the functionality, thus he completed the given work. He developed all this independently and I met him only few times when we discussed what to do next. He was able to pick up the ideas very quickly and he implemented and verified everything before proceeding to next ideas. Overall, I am really happy on his performance and I have hired him for three months to synthesize his design on ASIC technology and carry out power analysis. I expect we will write a scientific article out of his work once he has the numbers available.

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