Versatile Chirp Sine Generator on Fix-point FPGA
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This paper deals with a logarithmic and a linear chirp sine generation on a fixed-point FPGA mainly for vibration testing, nevertheless, the generator can also be used in other areas. A basic overview of the logarithmic chirp sine signal is provided. Then, methods of software signal generation as well as different hardware platforms are briefly described and their pros and cons are mentioned. A DDS generator on FPGA needs the phase difference between samples as an input. This generation for the logarithm chirp sine signal is presented, and its resolution, errors and limitations on fixed-point arithmetic are revealed. Our implementation runs on Compact RIO 9067, uses 32-bit fixed-point and is able to generate linear and logarithm chirp signals from 10 Hz to 7 kHz with a minimum chirp speed of 1 oct/min.
Document typePeer reviewed
Document versionFinal PDF
SourceActa Polytechnica (on-line). 2020, vol. 60, issue 6, p. 462-468.