Acceleration Unit for HTTP Headers Identification in FPGA
Alternative metrics PlumXhttp://hdl.handle.net/11012/42922
MetadataShow full item record
This paper presents a hardware accelerated identification of HTTP protocol headers, since HTTP is the most used protocol on the Internet. We have designed a hardware architecture, which will be used for detection of HTTP header in each packet. Architecture will be able to achieve the throughput needed for monitoring of 100 Gb/s networks. Nondeterministic finite automata and massive parallelism is used for pattern match.
Document typePeer reviewed
SourceProceedings of the 21st Conference STUDENT EEICT 2015. s. 34-36. ISBN 978-80-214-5148-3
- Student EEICT 2015