Analysis of Minimal LDPC Decoder System on a Chip Implementation
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This paper presents a practical method of potential replacement of several different Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes with one, with the intention of saving as much memory as required to implement the LDPC encoder and decoder in a memory-constrained System on a Chip (SoC). The presented method requires only a very small modification of the existing encoder and decoder, making it suitable for utilization in a Software Defined Radio (SDR) platform. Besides the analysis of the effects of necessary variable-node value fixation during the Belief Propagation (BP) decoding algorithm, practical standard-defined code parameters are scrutinized in order to evaluate the feasibility of the proposed LDPC setup simplification. Finally, the error performance of the modified system structure is evaluated and compared with the original system structure by means of simulation.
KeywordsLDPC code shortening, System on a Chip, fixed nodes decoder, Adaptive Coding and Modulation
Document typePeer reviewed
Document versionFinal PDF
SourceRadioengineering. 2015 vol. 24, č. 3, s. 783-790. ISSN 1210-2512
- 2015/3