Basic Block of Pipelined ADC Design Requirements
Alternativní metriky PlumXhttp://hdl.handle.net/11012/56824
MetadataZobrazit celý záznam
The paper describes design requirements of a basic stage (called MDAC - Multiplying Digital-to- Analog Converter) of a pipelined ADC. There exist error sources such as finite DC gain of opamp, capacitor mismatch, thermal noise, etc., arising when the switched capacitor (SC) technique and CMOS technology are used. These non-idealities are explained and their influences on overall parameters of a pipelined ADC are studied. The pipelined ADC including non-idealities was modeled in MATLAB - Simulink simulation environment.
Zdrojový dokumentRadioengineering. 2011, vol. 20, č. 1, s. 234-238. ISSN 1210-2512
- 2011/1