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dc.contributor.authorLiang, W.
dc.contributor.authorSun, X.
dc.contributor.authorRuan, Z.
dc.contributor.authorLong, J.
dc.contributor.authorWu, C.
dc.date.accessioned2016-02-29T13:46:27Z
dc.date.available2016-02-29T13:46:27Z
dc.date.issued2011-06cs
dc.identifier.citationRadioengineering. 2011, vol. 20, č. 2, s. 533-539. ISSN 1210-2512cs
dc.identifier.issn1210-2512
dc.identifier.urihttp://hdl.handle.net/11012/56871
dc.description.abstractIn Very Large Scale Integrated Circuits (VLSI) design, the existing Design-for-Test(DFT) based watermarking techniques usually insert watermark through reordering scan cells, which causes large resource overhead, low security and coverage rate of watermark detection. A novel scheme was proposed to watermark multiple scan chains in DFT for solving the problems. The proposed scheme adopts DFT scan test model of VLSI design, and uses a Linear Feedback Shift Register (LFSR) for pseudo random test vector generation. All of the test vectors are shifted in scan input for the construction of multiple scan chains with minimum correlation. Specific registers in multiple scan chains will be changed by the watermark circuit for watermarking the design. The watermark can be effectively detected without interference with normal function of the circuit, even after the chip is packaged. The experimental results on several ISCAS benchmarks show that the proposed scheme has lower resource overhead, probability of coincidence and higher coverage rate of watermark detection by comparing with the existing methods.en
dc.formattextcs
dc.format.extent533-539cs
dc.format.mimetypeapplication/pdfen
dc.language.isoencs
dc.publisherSpolečnost pro radioelektronické inženýrstvícs
dc.relation.ispartofRadioengineeringcs
dc.relation.urihttp://www.radioeng.cz/fulltexts/2011/11_02_533_539.pdfcs
dc.rightsCreative Commons Attribution 3.0 Unported Licenseen
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/en
dc.subjectIP reuseen
dc.subjectVLSIen
dc.subjectDFTen
dc.subjectLFSRen
dc.subjectmultiple scan chainsen
dc.titleA Sequential Circuit-Based IP Watermarking Algorithm for Multiple Scan Chains in Design-for-Testen
eprints.affiliatedInstitution.facultyFakulta eletrotechniky a komunikačních technologiícs
dc.coverage.issue2cs
dc.coverage.volume20cs
dc.rights.accessopenAccessen
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen


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Except where otherwise noted, this item's license is described as Creative Commons Attribution 3.0 Unported License