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dc.contributor.authorKubicek, M.
dc.contributor.authorKolka, Zdeněk
dc.date.accessioned2016-03-11T09:17:14Z
dc.date.available2016-03-11T09:17:14Z
dc.date.issued2010-04cs
dc.identifier.citationRadioengineering. 2010, vol. 19, č. 1, s. 74-78. ISSN 1210-2512cs
dc.identifier.issn1210-2512
dc.identifier.urihttp://hdl.handle.net/11012/56965
dc.description.abstractThe paper is focused on the optimization and implementation of fully digital feed-forward blind oversampling CDR (BO-CDR). Two new phase-decision algorithms are proposed. Their complexity is very low, enabling a very simple and fast implementation even in FPGA, which was used as a development platform as well as a target device for the BO-CDR block. The FPGA-based optimization gave the opportunity to perform on-the-fly optimization under real conditions of target link. This greatly shortened the development time as there were no errors caused by inaccurate simulation models. Measurement results obtained on real links are included showing the jitter tolerance of the proposed algorithms to be comparable to the performance of modern PLL-based CDRs.en
dc.formattextcs
dc.format.extent74-78cs
dc.format.mimetypeapplication/pdfen
dc.language.isoencs
dc.publisherSpolečnost pro radioelektronické inženýrstvícs
dc.relation.ispartofRadioengineeringcs
dc.relation.urihttp://www.radioeng.cz/fulltexts/2010/10_01_074_078.pdfcs
dc.rightsCreative Commons Attribution 3.0 Unported Licenseen
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/en
dc.subjectBlind Oversampling CDRen
dc.subjectFPGAen
dc.subjectjitteren
dc.titleBlind Oversampling Data Recovery with Low Hardware Complexityen
eprints.affiliatedInstitution.facultyFakulta eletrotechniky a komunikačních technologiícs
dc.coverage.issue1cs
dc.coverage.volume19cs
dc.rights.accessopenAccessen
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen


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