VHDL Model of Electronic-Lock System
Аннотации
The paper describes the design of an electronic-lock system which was completed as part of the Basic VHDL course in the Department of Control and Measurement Faculty of Electrical Engineering and Informatics, Technical University of Ostrava, Czech Republic in co-operation with the Department if Electronic Engineering, University of Hull, Great Britain in the frame of TEMPUS project no. S_JEP/09468-95.
Document type
Peer reviewedDocument version
Final PDFSource
Radioengineering. 2000, vol. 9, č. 1, s. 4-8. ISSN 1210-2512http://www.radioeng.cz/fulltexts/2000/00_01_04_08.pdf
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- 2000/1 [11]
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