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dc.contributor.authorVlcek, K.
dc.contributor.authorBannister, B. R.
dc.contributor.authorMiklik, D.
dc.contributor.authorBell, I. M.
dc.contributor.authorBartsch, E.
dc.contributor.authorNoga, J.
dc.date.accessioned2016-05-02T12:41:41Z
dc.date.available2016-05-02T12:41:41Z
dc.date.issued2000-04cs
dc.identifier.citationRadioengineering. 2000, vol. 9, č. 1, s. 4-8. ISSN 1210-2512cs
dc.identifier.issn1210-2512
dc.identifier.urihttp://hdl.handle.net/11012/58215
dc.description.abstractThe paper describes the design of an electronic-lock system which was completed as part of the Basic VHDL course in the Department of Control and Measurement Faculty of Electrical Engineering and Informatics, Technical University of Ostrava, Czech Republic in co-operation with the Department if Electronic Engineering, University of Hull, Great Britain in the frame of TEMPUS project no. S_JEP/09468-95.en
dc.formattextcs
dc.format.extent4-8cs
dc.format.mimetypeapplication/pdfen
dc.language.isoencs
dc.publisherSpolečnost pro radioelektronické inženýrstvícs
dc.relation.ispartofRadioengineeringcs
dc.relation.urihttp://www.radioeng.cz/fulltexts/2000/00_01_04_08.pdfcs
dc.rightsCreative Commons Attribution 3.0 Unported Licenseen
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/en
dc.subjectsystem designen
dc.subjectfinite state machineen
dc.subjectbehavioural VHDL modellingen
dc.subjectFPGA implementationen
dc.titleVHDL Model of Electronic-Lock Systemen
eprints.affiliatedInstitution.facultyFakulta eletrotechniky a komunikačních technologiícs
dc.coverage.issue1cs
dc.coverage.volume9cs
dc.rights.accessopenAccessen
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen


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