Synchronous Counters Implemented in the PLD Devices
Abstrakt
The implementability of synchronous counters in the Programmable Logic Devices (PLD) is discussed in this paper. The most commonly used counters are analysed from this point of view. The expressions for their individual bits are given and the number of product terms is derived to allow to estimate the size of the particular counter which can be implemented in the chosen PLD.
Klíčová slova
programmable logic devices, synchronous counters, product terms, implementabilityTrvalý odkaz
http://hdl.handle.net/11012/58254Typ dokumentu
Recenzovaný dokumentVerze dokumentu
Finální verze PDFZdrojový dokument
Radioengineering. 1999, vol. 8, č. 1, s. 14-18. ISSN 1210-2512http://www.radioeng.cz/fulltexts/1999/99_01_03.pdf
Kolekce
- 1999/1 [10]
Citace PRO
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