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dc.contributor.authorKolouch, J.
dc.date.accessioned2016-05-03T10:52:16Z
dc.date.available2016-05-03T10:52:16Z
dc.date.issued1999-04cs
dc.identifier.citationRadioengineering. 1999, vol. 8, č. 1, s. 14-18. ISSN 1210-2512cs
dc.identifier.issn1210-2512
dc.identifier.urihttp://hdl.handle.net/11012/58254
dc.description.abstractThe implementability of synchronous counters in the Programmable Logic Devices (PLD) is discussed in this paper. The most commonly used counters are analysed from this point of view. The expressions for their individual bits are given and the number of product terms is derived to allow to estimate the size of the particular counter which can be implemented in the chosen PLD.en
dc.formattextcs
dc.format.extent14-18cs
dc.format.mimetypeapplication/pdfen
dc.language.isoencs
dc.publisherSpolečnost pro radioelektronické inženýrstvícs
dc.relation.ispartofRadioengineeringcs
dc.relation.urihttp://www.radioeng.cz/fulltexts/1999/99_01_03.pdfcs
dc.rightsCreative Commons Attribution 3.0 Unported Licenseen
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/en
dc.subjectprogrammable logic devicesen
dc.subjectsynchronous countersen
dc.subjectproduct termsen
dc.subjectimplementabilityen
dc.titleSynchronous Counters Implemented in the PLD Devicesen
eprints.affiliatedInstitution.facultyFakulta eletrotechniky a komunikačních technologiícs
dc.coverage.issue1cs
dc.coverage.volume8cs
dc.rights.accessopenAccessen
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen


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