VLSI Implementation of Fixed-Point Lattice Wave Digital Filters for Increased Sampling Rate
Alternative metrics PlumXhttp://hdl.handle.net/11012/63768
MetadataShow full item record
Low complexity and high speed are the key requirements of the digital filters. These filters can be realized using allpass filters. In this paper, design and minimum multiplier implementation of a fixed point lattice wave digital filter (WDF) based on three port parallel adaptor allpass structure is proposed. Here, the second-order allpass sections are implemented with three port parallel adaptor allpass structures. A design-level area optimization is done by converting constant multipliers into shifts and adds using canonical signed digit (CSD) techniques. The proposed implementation reduces the latency of the critical loop by reducing the number of components (adders and multipliers). Three design examples are included to analyze the effectiveness of the proposed approach. These are implemented in verilog HDL language and mapped to a standard cell library in a 0.18 μm CMOS process. The functionality of the implementations have been verified by applying number of different input vectors. Results and simulations demonstrate that the proposed design method leads to an efficient lattice WDF in terms of maximum sampling frequency. The cost to pay is small area overhead. The postlayout simulations have been done by HSPICE with CMOS transistors.
KeywordsVLSI implementation, lattice wave digital filters, three port adaptor, canonical signed digit coefficient, fixed point arithmetic
Document typePeer reviewed
SourceRadioengineering. 2016 vol. 25, č. 4, s. 821-829. ISSN 1210-2512
- 2016/4