Show simple item record

dc.contributor.authorYasir, A.
dc.contributor.authorWu, N.
dc.contributor.authorChen, X.
dc.contributor.authorRehan Yahya, M.
dc.date.accessioned2018-06-18T12:49:19Z
dc.date.available2018-06-18T12:49:19Z
dc.date.issued2018-06cs
dc.identifier.citationRadioengineering. 2018 vol. 27, č. 2, s. 541-548. ISSN 1210-2512cs
dc.identifier.issn1210-2512
dc.identifier.urihttp://hdl.handle.net/11012/83038
dc.description.abstractIn this paper, state-of-the-art hardware implementations of MISTY1 block cipher are presented for area-constrained wireless applications. The proposed MISTY1 architectures are characterized of highly optimized transformation functions i.e. FL and {FO-XOR-EKG}. The FL function re-utilizes logic AND-OR-XOR combinations whereas {FO-XOR-EKG} function explores 2 × compact design schemes for s-boxes implementation. A Combined Substitution Unit (CSU) and threshold area implementation are proposed for s-boxes based on Boolean reductions and Common Sub-expression Eliminations (CSEs). Besides, {FO-XOR-EKG} function is designed for manifold operations of FO / FI functions, 32-bit XOR operation and extended key generation thereby reducing the area. Hardware implementations on ASIC 180nm, 1.8V standard library cell realized compact and threshold MISTY1 designs constituting 1853 and 1546 NAND gates with throughput values of 41.6 Mbps and 4.72 Mbps respectively. A comprehensive comparison with existing cryptographic hardware designs establishes that the proposed MISTY1 architectures are the most area-efficient implementations till date.en
dc.formattextcs
dc.format.extent541-548cs
dc.format.mimetypeapplication/pdfen
dc.language.isoencs
dc.publisherSpolečnost pro radioelektronické inženýrstvícs
dc.relation.ispartofRadioengineeringcs
dc.relation.urihttps://www.radioeng.cz/fulltexts/2018/18_02_0541_0548.pdfcs
dc.rightsCreative Commons Attribution 4.0 Internationalen
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/en
dc.subjectMISTY1en
dc.subjectASICsen
dc.subjectwireless communicationsen
dc.subjectS-boxen
dc.subjectcommon sub-expression eliminationen
dc.titleArea-Efficient Hardware Architectures of MISTY1 Block Cipheren
eprints.affiliatedInstitution.facultyFakulta eletrotechniky a komunikačních technologiícs
dc.coverage.issue2cs
dc.coverage.volume27cs
dc.identifier.doi10.13164/re.2018.0541en
dc.rights.accessopenAccessen
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record

Creative Commons Attribution 4.0 International
Except where otherwise noted, this item's license is described as Creative Commons Attribution 4.0 International