Designing series of fractional-order elements
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Date
2021-03-08
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Mark
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SPRINGER
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Abstract
In this paper we propose an efficient approach to design fractional-order elements' (FOEs) series, while using a very limited set of "seed" FOEs. The proposed approach follows the idea of general immittance inverter/converter, whereas a suitable circuit solution employing operational transconductance amplifiers is also presented and can be used for the design of grounded FOEs with the fractional order alpha being in the range [-2,2]. The proposed circuit may simply be extended to design fractional-order elements from wider range of alpha to follow designers' requirements. To show the efficiency of the described technique, the use of only up to two "seed" FOEs with properly selected fractional order alpha seed as passive elements results in the design of a series of 17 FOEs with different alpha being in the range [-2,2]. Cadence post-layout simulation results are presented that prove operability and robustness of our design concept. Basic fractional 1.75-order low-pass filter is also presented to show the utilization of a FOE being implemented by the proposed GIC.
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ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING. 2021, vol. 106, issue 3, p. 553-563.
https://link.springer.com/content/pdf/10.1007/s10470-021-01811-4.pdf
https://link.springer.com/content/pdf/10.1007/s10470-021-01811-4.pdf
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Peer-reviewed
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en
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(C) SPRINGER