Fully CMOS Memristor Based Chaotic Circuit
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Date
2014-12
Authors
ORCID
Advisor
Referee
Mark
Journal Title
Journal ISSN
Volume Title
Publisher
Společnost pro radioelektronické inženýrství
Abstract
This paper demonstrates the design of a fully CMOS chaotic circuit consisting of only DDCC based memristor and inductance simulator. Our design is composed of these active blocks using CMOS 0.18 µm process technology with symmetric ±1.25 V supply voltages. A new single DDCC+ based topology is used as the inductance simulator. Simulation results verify that the design proposed satisfies both memristor properties and the chaotic behavior of the circuit. Simulations performed illustrate the success of the proposed design for the realization of CMOS based chaotic applications.
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Citation
Radioengineering. 2014, vol. 23, č. 4, s. 1140-1149. ISSN 1210-2512
http://www.radioeng.cz/fulltexts/2014/14_04_1140_1149.pdf
http://www.radioeng.cz/fulltexts/2014/14_04_1140_1149.pdf
Document type
Peer-reviewed
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Published version
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en