Clock Domain Crossing Interfaces
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Date
2015
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Mark
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Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií
Abstract
This work presents an easy-to-use library of clock domain crossing modules and a methodology for it's use. These crossings are inevitable in moderately complex firmware designs. Incorrectly implemented clock domain crossing modules can lead to data corruption or data loss. For correct functionality of these crossings it is necessary to apply correct constraints. Automatic application of contraints is a part of the created library. Its easy use is also supported by the methodology for selection of correct clock domain crossing module in the form of a decision tree.
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Proceedings of the 21st Conference STUDENT EEICT 2015. s. 37-39. ISBN 978-80-214-5148-3
http://www.feec.vutbr.cz/EEICT/
http://www.feec.vutbr.cz/EEICT/
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Peer-reviewed
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cs
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© Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií