A Chaotic IP Watermarking in Physical Layout Level Based on FPGA
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Date
2011-04
ORCID
Advisor
Referee
Mark
Journal Title
Journal ISSN
Volume Title
Publisher
Společnost pro radioelektronické inženýrství
Abstract
A new chaotic map based IP (Intellectual Property) watermarking scheme at physical design level is presented. An encrypted watermark is embedded into the physical layout of a circuit by configuring LUT (Lookup Table) as specific functions when it is placed and routed onto the FPGA (Field-Programmable Gate Array). The main contribution is the use of multiple chaotic maps in the processes of watermark design and embedding, which efficiently improves the security of watermark. A hashed chaotic sequence is used to scramble the watermark. Secondly, two pseudo-random sequences are generated by using chaotic maps. One is used to determine unused LUT locations, and the other divides the watermark into groups. The watermark identifies original owner and is difficult to detect. This scheme was tested on a Xilinx Virtex XCV600-6bg432 FPGA. The experimental results show that our method has low impact on functionality, short path delay and high robustness in comparison with other methods.
Description
Citation
Radioengineering. 2011, vol. 20, č. 1, s. 118-125. ISSN 1210-2512
http://www.radioeng.cz/fulltexts/2011/11_01_118_125.pdf
http://www.radioeng.cz/fulltexts/2011/11_01_118_125.pdf
Document type
Peer-reviewed
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Published version
Date of access to the full text
Language of document
en