A Sequential Circuit-Based IP Watermarking Algorithm for Multiple Scan Chains in Design-for-Test
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Date
2011-06
ORCID
Advisor
Referee
Mark
Journal Title
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Volume Title
Publisher
Společnost pro radioelektronické inženýrství
Abstract
In Very Large Scale Integrated Circuits (VLSI) design, the existing Design-for-Test(DFT) based watermarking techniques usually insert watermark through reordering scan cells, which causes large resource overhead, low security and coverage rate of watermark detection. A novel scheme was proposed to watermark multiple scan chains in DFT for solving the problems. The proposed scheme adopts DFT scan test model of VLSI design, and uses a Linear Feedback Shift Register (LFSR) for pseudo random test vector generation. All of the test vectors are shifted in scan input for the construction of multiple scan chains with minimum correlation. Specific registers in multiple scan chains will be changed by the watermark circuit for watermarking the design. The watermark can be effectively detected without interference with normal function of the circuit, even after the chip is packaged. The experimental results on several ISCAS benchmarks show that the proposed scheme has lower resource overhead, probability of coincidence and higher coverage rate of watermark detection by comparing with the existing methods.
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Citation
Radioengineering. 2011, vol. 20, č. 2, s. 533-539. ISSN 1210-2512
http://www.radioeng.cz/fulltexts/2011/11_02_533_539.pdf
http://www.radioeng.cz/fulltexts/2011/11_02_533_539.pdf
Document type
Peer-reviewed
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Published version
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Language of document
en