Test Methods of PAL-, PLA-, and MAPL- Structures

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dc.contributor.authorVlcek, K.
dc.coverage.issue3cs
dc.coverage.volume4cs
dc.date.accessioned2016-05-06T11:46:20Z
dc.date.available2016-05-06T11:46:20Z
dc.date.issued1995-09cs
dc.description.abstractThe architecture of various programmable logic arrays such as PAL (Programmable Array Logic), PLA (Programmable Logic Array) and MAPL (Multiple Array Programmable Logic) differ slightly in interconnection. The introduced types of devices are called PLD (Programmable Logic Devices). It is a bulk of programmable AND functions (product terms), and OR functions. The whole circuit structure is completed by input/output or dedicated output macrocells allowing to do the minimization of product term number. PLD's internal AND-array, and OR-array differs from the discrete logic AND, and OR devices whereas the functions are similar. The troubleshooting of these devices differs too.en
dc.formattextcs
dc.format.extent16-19cs
dc.format.mimetypeapplication/pdfen
dc.identifier.citationRadioengineering. 1995, vol. 4, č. 3, s. 16-19. ISSN 1210-2512cs
dc.identifier.issn1210-2512
dc.identifier.urihttp://hdl.handle.net/11012/58461
dc.language.isoencs
dc.publisherSpolečnost pro radioelektronické inženýrstvícs
dc.relation.ispartofRadioengineeringcs
dc.relation.urihttp://www.radioeng.cz/fulltexts/1995/95_03_04.pdfcs
dc.rightsCreative Commons Attribution 3.0 Unported Licenseen
dc.rights.accessopenAccessen
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/en
dc.subjectPALen
dc.subjectPLAen
dc.subjectMAPLen
dc.subjectprogrammable logic devicesen
dc.titleTest Methods of PAL-, PLA-, and MAPL- Structuresen
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
eprints.affiliatedInstitution.facultyFakulta eletrotechniky a komunikačních technologiícs
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