Analysis for Design and Transformation of Autosynchronous State Machines

dc.contributor.authorKovac, Michal
dc.contributor.authorKolouch, Jaromir
dc.coverage.issue1cs
dc.coverage.volume19cs
dc.date.accessioned2016-03-11T09:17:15Z
dc.date.available2016-03-11T09:17:15Z
dc.date.issued2010-04cs
dc.description.abstractThe paper deals with design and transformation methodology of autosynchronous state machines. The result is the design methodology for autosynchronous state machines with one-hot and Gray encodings. On the basis of their simulation models the timing parameters are defined and conditions for the correct behavior are pointed out. In order to simplify the design of these state machines, the transformation methodology of synchronous state machine in VHDL at RTL level to autosynchronous state machine is designed. These transformed state machines are compared in their chip area, power consumption and timing.en
dc.formattextcs
dc.format.extent99-104cs
dc.format.mimetypeapplication/pdfen
dc.identifier.citationRadioengineering. 2010, vol. 19, č. 1, s. 99-104. ISSN 1210-2512cs
dc.identifier.issn1210-2512
dc.identifier.urihttp://hdl.handle.net/11012/56968
dc.language.isoencs
dc.publisherSpolečnost pro radioelektronické inženýrstvícs
dc.relation.ispartofRadioengineeringcs
dc.relation.urihttp://www.radioeng.cz/fulltexts/2010/10_01_099_104.pdfcs
dc.rightsCreative Commons Attribution 3.0 Unported Licenseen
dc.rights.accessopenAccessen
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/en
dc.subjectAutosynchronous circuiten
dc.subjectstate machineen
dc.subjectVHDLen
dc.subjectRTLen
dc.subjecttransformationen
dc.subjectone-hot encodingen
dc.subjectGray encodingen
dc.titleAnalysis for Design and Transformation of Autosynchronous State Machinesen
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
eprints.affiliatedInstitution.facultyFakulta eletrotechniky a komunikačních technologiícs
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