Low-Voltage MOS Current Mode Logic Multiplexer

dc.contributor.authorGupta, Kirti
dc.contributor.authorPandey, Neeta
dc.contributor.authorGupta, Maneesha
dc.coverage.issue1cs
dc.coverage.volume22cs
dc.date.accessioned2015-01-20T14:14:18Z
dc.date.available2015-01-20T14:14:18Z
dc.date.issued2013-04cs
dc.description.abstractIn this paper, a new low-voltage MOS current mode logic (MCML) multiplexer based on the triple-tail cell concept is proposed. An analytical model for static parameters is formulated and is applied to develop a design approach for the proposed low-voltage MCML multiplexer. The delay of the proposed low-voltage MCML multiplexer is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage MCML multiplexer is analyzed for the three design cases namely high-speed, power-efficient, and low-power. Finally, a comparison in performance of the proposed low-voltage MCML multiplexer with the traditional MCML multiplexer is carried out for all the cases.en
dc.formattextcs
dc.format.extent259-268cs
dc.format.mimetypeapplication/pdfen
dc.identifier.citationRadioengineering. 2013, vol. 22, č. 1, s. 259-268. ISSN 1210-2512cs
dc.identifier.issn1210-2512
dc.identifier.urihttp://hdl.handle.net/11012/36845
dc.language.isoencs
dc.publisherSpolečnost pro radioelektronické inženýrstvícs
dc.relation.ispartofRadioengineeringcs
dc.relation.urihttp://www.radioeng.cz/fulltexts/2013/13_01_0259_0268.pdfcs
dc.rightsCreative Commons Attribution 3.0 Unported Licenseen
dc.rights.accessopenAccessen
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/en
dc.subjectMOS current mode logicen
dc.subjectlow-voltageen
dc.subjecttriple-tail cellen
dc.titleLow-Voltage MOS Current Mode Logic Multiplexeren
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
eprints.affiliatedInstitution.facultyFakulta eletrotechniky a komunikačních technologiícs
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