Basic Block of Pipelined ADC Design Requirements

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dc.contributor.authorKledrowetz, Vilem
dc.contributor.authorHaze, Jiri
dc.coverage.issue1cs
dc.coverage.volume20cs
dc.date.accessioned2016-02-26T08:17:27Z
dc.date.available2016-02-26T08:17:27Z
dc.date.issued2011-04cs
dc.description.abstractThe paper describes design requirements of a basic stage (called MDAC - Multiplying Digital-to- Analog Converter) of a pipelined ADC. There exist error sources such as finite DC gain of opamp, capacitor mismatch, thermal noise, etc., arising when the switched capacitor (SC) technique and CMOS technology are used. These non-idealities are explained and their influences on overall parameters of a pipelined ADC are studied. The pipelined ADC including non-idealities was modeled in MATLAB - Simulink simulation environment.en
dc.formattextcs
dc.format.extent234-238cs
dc.format.mimetypeapplication/pdfen
dc.identifier.citationRadioengineering. 2011, vol. 20, č. 1, s. 234-238. ISSN 1210-2512cs
dc.identifier.issn1210-2512
dc.identifier.urihttp://hdl.handle.net/11012/56824
dc.language.isoencs
dc.publisherSpolečnost pro radioelektronické inženýrstvícs
dc.relation.ispartofRadioengineeringcs
dc.relation.urihttp://www.radioeng.cz/fulltexts/2011/11_01_234_238.pdfcs
dc.rightsCreative Commons Attribution 3.0 Unported Licenseen
dc.rights.accessopenAccessen
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/en
dc.subjectPipelined ADCen
dc.subjectMDACen
dc.subjectSC techniqueen
dc.subjectMATLAB modelen
dc.subjectthermal noiseen
dc.subjectopampen
dc.titleBasic Block of Pipelined ADC Design Requirementsen
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
eprints.affiliatedInstitution.facultyFakulta eletrotechniky a komunikačních technologiícs
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