Now showing items 1-2 of 2
Efficient Architecture and Implementation of Vector Median Filter in Co-Design Context
(Společnost pro radioelektronické inženýrství, 2007-09)
This work presents an efficient fast parallel architecture of the Vector Median Filter (VMF) using combined hardware/software (HW/SW) implementation. The hardware part of the system is implemented using VHDL language, ...
Implementation and Evaluation of Power Consumption of an Iris Pre-processing Algorithm on Modern FPGA
(Společnost pro radioelektronické inženýrství, 2008-12)
In this article, the efficiency and applicability of several power reduction techniques applied on a modern 65nm FPGA is described. For image erosion and dilation algorithms, two major solutions were tested and compared ...