Digital Predistorter Design Using a Reduced Volterra Model to Linearize GaN RF Power Amplifiers
Résumé
In this paper, a novel method for reducing a Simplified Volterra Series (SVS) model size is proposed for GaN RF Power Amplifier (PA) Digital Predistorter (DPD) design. Using the SVS-modified model, the number of coefficients needed for the PA behavioral modeling and predistortion can be reduced by 60 % while maintaining acceptable performances. Simulation and implementation tests are performed for a Class AB GaN PA and Doherty GaN PA using a 20-MHz Long Term Evolution-Advanced (LTE-A) signal. The Adjacent Channel Power Ratio (ACPR) attains -40 dB and -41 dB for the Doherty and Class AB GaN PAs, respectively. The implementation complexity is also studied and the obtained results prove the capability of the proposed model to linearize PA using 3% of the Slice LUTs and 87% of the DSP48E1 available in the Xilinx Zynq-7000 FPGA.
Keywords
RF power amplifier, digital predistortion (DPD), simplified Volterra series, estimation algorithms, look up table (LUT), least squares algorithmsDocument type
Peer reviewedDocument version
Final PDFSource
Radioengineering. 2018 vol. 27, č. 3, s. 909-916. ISSN 1210-2512https://www.radioeng.cz/fulltexts/2018/18_03_0909_0916.pdf
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