Remote Memory Access Protocol Controller For Spacewire Network

Walletzký, Ondřej

Remote Memory Access Protocol Controller For Spacewire Network

but.event.date	27.04.2017	cs
but.event.title	Student EEICT 2017	cs
dc.contributor.author	Walletzký, Ondřej
dc.date.accessioned	2020-05-07T09:40:28Z
dc.date.available	2020-05-07T09:40:28Z
dc.date.issued	2017	cs
dc.description.abstract	This article describes design and implementation of Remote Memory Access Protocol controller, namely the initiator module specified in the ECSS-E-ST-50-52C standard. It provides general description of its architecture and describes some of its subcomponents. Finally, it summarizes resource utilization and maximum theoretical clock frequency for different configurations when synthesized for Spartan-3 FPGA chip.	en
dc.format	text	cs
dc.format.extent	251-253	cs
dc.format.mimetype	application/pdf	en
dc.identifier.citation	Proceedings of the 23st Conference STUDENT EEICT 2017. s. 251-253. ISBN 978-80-214-5496-5	cs
dc.identifier.isbn	978-80-214-5496-5
dc.identifier.uri	http://hdl.handle.net/11012/187098
dc.language.iso	cs	cs
dc.publisher	Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií	cs
dc.relation.ispartof	Proceedings of the 23st Conference STUDENT EEICT 2017	en
dc.relation.uri	http://www.feec.vutbr.cz/EEICT/	cs
dc.rights	© Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií	cs
dc.rights.access	openAccess	en
dc.subject	RMAP	en
dc.subject	SpaceWire	en
dc.subject	VHDL	en
dc.subject	FPGA	en
dc.subject	AMBA	en
dc.subject	AHB	en
dc.title	Remote Memory Access Protocol Controller For Spacewire Network	en
dc.type.driver	conferenceObject	en
dc.type.status	Peer-reviewed	en
dc.type.version	publishedVersion	en
eprints.affiliatedInstitution.department	Fakulta elektrotechniky a komunikačních technologií	cs

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